On Tue, Nov 27, 2018 at 2:16 AM Leonard Crestez <leonard.crestez@xxxxxxx> wrote:
>
> On 11/26/18 8:24 PM, Andrey Smirnov wrote:
> > On Tue, Nov 20, 2018 at 2:49 AM Leonard Crestez <leonard.crestez@xxxxxxx> wrote:
> >> On Sat, 2018-11-17 at 10:12 -0800, Andrey Smirnov wrote:
>
> >>> + if (of_property_read_u32_array(
> >>> + node, "fsl,gpr12-device-type",
> >>> + imx6_pcie->device_type,
> >>> + ARRAY_SIZE(imx6_pcie->device_type))) {
> >>> + dev_err(dev, "Failed to get device type
> >>> mask/value\n");
> >>> + return -EINVAL;
> >>> + }
> >>
> >> The device type can be set on multiple SOCs, why are you adding a
> >> mandatory property only for 8m?
> >
> > My thinking was that other SoCs don't really have two controllers, so
> > they don't really need to have that property, but, more importantly,
> > not forcing them to have this property should preserve backwards
> > compatibility with old DTBs.
>
> The "device_type" registers determine Root Complex versus End Point
> mode. This is not yet supported on imx in upstream but it can be done on
> many soc versions.
>
Yeah, I am aware, I wasn't really trying to make it possible to
configure IP block to be a EP, that is just an unavoidable consequence
of the approach taken.
> Looking at other pcie controllers (and dwc core) this is normally done
> with a different compatible string with an "-ep" suffix. It feels wrong
> to expose bitmasks and values directly in DT instead.
>
> For this patch you should probably just hardcode RC mode.
Hmm, given how the mask/value have to be different for each
controller, the only way to hardcode it that I can think of would be
to change the property pass a bit offset instead of mask/value pair.
Is that what you are suggesting?
Thanks,
Andrey Smirnov
