Re: [PATCH 0/3] PCI: designware: Fixing MSI handling flow

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On Wed, 2018-11-14 at 22:07 +0000, Marc Zyngier wrote:
> On Wed, 14 Nov 2018 18:28:05 +0000,
> Trent Piepho <tpiepho@xxxxxxxxxx> wrote:
> > 
> > 
> > The new domain stuff does not appear to integrate into the existing irq
> > framework perfectly.  My interrupt has changed from MSI #1 to MSI
> > #524288.  Not the most user friendly number.
> 
> It is not supposed to be user friendly. It is not even supposed to be
> interpreted by anyone. And if you print it in hex, you'll find that it
> *is* actually useful.

The GPCv2 values match those in the datasheet.  This is very handy!

domain:  :soc:aips-bus@30800000:pcie@33800000-3
 hwirq:   0x80000
 chip:    PCI-MSI
  flags:   0x20
             IRQCHIP_ONESHOT_SAFE
 parent:
    domain:  :soc:aips-bus@30800000:pcie@33800000
     hwirq:   0x1
     chip:    DWPCI-MSI
      flags:   0x0

It's not clear to me what these two domains are for.  Perhaps if I had
multiple busses or multiple ports it would be.  I'm assuming the offset
is based on 2048 MSI-Xs per function, 8 functions per device, and 32
devices per bus.  So perhaps this means this is MSI 0 on bus 1 of the
controller.




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