All,
I'm curious what is the expected order of boot/configuration/enumeration
for Linux's PCIe endpoint support. I had assumed it was the following:
1) Boot the PCIe endpoint system fully.
2) Use configfs to create a PCIe endpoint function, configure it, and
bind it to the relevant endpoint controller. The endpoint is now fully
configured/enabled to respond to configuration/... accesses.
3) Boot the PCIe root port system.
4) At some point during boot of the root port system, it will perform
PCIe enumeration, and hence detect the "SW-defined" endpoint.
However, with our hardware (an implementation of the Synopsis DWC PCIe
controller), this order of events does not work. That's because in step
2 above, the configuration is written directly to the endpoint
controller as it is performed (e.g. device/vendor ID, BAR size, etc.).
At least in our hardware, the relevant registers are not accessible
until PEXCLK is provided by the root port, which only happens in step 3.
Do other implementations of DWC (or indeed other endpoint controllers)
not have this restriction? Or, are we expected to boot the two systems
in one of the following manners:
Option A:
1) Power on the root port system so that PEXCLK is available. The root
port software can boot in parallel with the steps below, but must not
perform PCIe enumeration (or if it does, it won't find anything).
2) Fully configure all aspects of the PCIe endpoint (PCIe header info
like vendor, device ID, BAR size/enable, iATU entries, SMMU, etc.), and
enable the endpoint controller to respond to link-up and enumeration events.
3) Signal PCIe hotplug from the endpoint to the root port system.
4) The root port responds to hotplug, and performs PCIe enumeration; the
endpoint will respond fully since it’s pre-programmed.
Option B:
1) Power on the root port system so that PEXCLK is available. The root
port software must not boot at all, to prevent getting to the boot stage
where PCIe enumeration is performed.
2) Fully configure all aspects of the PCIe endpoint (PCIe header info
like vendor, device ID, BAR size/enable, iATU entries, SMMU, etc.) , and
enable the endpoint controller to respond to link-up and enumeration events.
3) Signal to the root port system (or some kind of system-level
management controller) that root port system boot can proceed.
4) The root system actually boots, and whenever the root port performs
PCIe enumeration as part of the standard initial boot sequence, the
endpoint will respond fully since it’s pre-programmed.
Thanks for any insight re: how this subsystem integrates with existing
supported hardware. Is there any publicly available hardware that is
supported by mainline Linux's PCIe endpoint support?
