The EP driver did not check the mask bit for each MSI before
sending it in raise_irq. This is now checked, and -EINVAL is
returned if masked.
Fixes: 37dddf14f1ae ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller")
Signed-off-by: Alan Douglas <adouglas@xxxxxxxxxxx>
---
drivers/pci/controller/pcie-cadence-ep.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index c3a0889..b762214 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -332,6 +332,11 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
if (!interrupt_num || interrupt_num > msi_count)
return -EINVAL;
+ /* Check whether MSI is masked */
+ data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_MASK_64);
+ if (data & (1 << (interrupt_num - 1)))
+ return -EINVAL;
+
/* Compute the data value to be written. */
data_mask = msi_count - 1;
data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
--
1.9.0
