On Wed, 26 Sep 2018 14:45:27 +0200 Joerg Roedel <joro@xxxxxxxxxx> wrote: > On Wed, Sep 26, 2018 at 11:20:34AM +0100, Jean-Philippe Brucker wrote: > > Yes, at the moment it's difficult to guess what device drivers will > > want, but I can imagine some driver offering SVA to userspace, while > > keeping a few PASIDs for themselves to map kernel memory. Or create > > mdev devices for virtualization while also allowing bare-metal SVA. > > So I think we should aim at enabling these use-cases in parallel, > > even if it doesn't necessarily need to be possible right now. > > Yeah okay, but allowing these use-cases in parallel basically > disallows giving any guest control over a device's pasid-table, no? > For VT-d 3 (which is the only revision to support PASID), PASID table is always controlled by the host driver. Guest SVA usage would bind PASID with gCR3. But I thought ARM (https://lkml.org/lkml/2018/9/18/1082) is using bind PASID table approach which gives guest control of the device PASID table. I don't know if that is intended for any parallel use of PASID on the same device. > I am just asking because I want to make up my mind about the necessary > extensions to the IOMMU-API. > One extension, we will need and being developed is bind_guest_pasid() for guest SVA usage. Usage: 1. guest allocate a system wide PASID for SVA 2. guest write PASID to its PASID table 3. PASID cache flush results in bind PASID (from guest) to device 4. Host IOMMU driver install gCR3s of the PASID to device PASID table (ops.bind_guest_pasid) Thanks, Jacob > > Regards, > > Joerg > [Jacob Pan]
