Re: [PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues

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Hi Daniel,

I love your patch! Perhaps something to improve:

[auto build test WARNING on pci/next]
[also build test WARNING on v4.19-rc1 next-20180831]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Daniel-Drake/PCI-add-prefetch-quirk-to-work-around-Asus-Nvidia-suspend-issues/20180901-043245
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: x86_64-randconfig-x000-201834 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   drivers/pci/quirks.c: In function 'quirk_asus_pci_prefetch':
>> drivers/pci/quirks.c:5134:6: warning: argument 1 null where non-null expected [-Wnonnull]
     if (strcmp(sys_vendor, "ASUSTeK COMPUTER INC.") != 0)
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   In file included from include/linux/uuid.h:20:0,
                    from include/linux/mod_devicetable.h:13,
                    from include/linux/pci.h:21,
                    from drivers/pci/quirks.c:18:
   include/linux/string.h:44:12: note: in a call to function 'strcmp' declared here
    extern int strcmp(const char *,const char *);
               ^~~~~~

vim +5134 drivers/pci/quirks.c

  4983	
  4984	/*
  4985	 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
  4986	 * NT endpoints via the internal switch fabric. These IDs replace the
  4987	 * originating requestor ID TLPs which access host memory on peer NTB
  4988	 * ports. Therefore, all proxy IDs must be aliased to the NTB device
  4989	 * to permit access when the IOMMU is turned on.
  4990	 */
  4991	static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
  4992	{
  4993		void __iomem *mmio;
  4994		struct ntb_info_regs __iomem *mmio_ntb;
  4995		struct ntb_ctrl_regs __iomem *mmio_ctrl;
  4996		struct sys_info_regs __iomem *mmio_sys_info;
  4997		u64 partition_map;
  4998		u8 partition;
  4999		int pp;
  5000	
  5001		if (pci_enable_device(pdev)) {
  5002			pci_err(pdev, "Cannot enable Switchtec device\n");
  5003			return;
  5004		}
  5005	
  5006		mmio = pci_iomap(pdev, 0, 0);
  5007		if (mmio == NULL) {
  5008			pci_disable_device(pdev);
  5009			pci_err(pdev, "Cannot iomap Switchtec device\n");
  5010			return;
  5011		}
  5012	
  5013		pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
  5014	
  5015		mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
  5016		mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
  5017		mmio_sys_info = mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
  5018	
  5019		partition = ioread8(&mmio_ntb->partition_id);
  5020	
  5021		partition_map = ioread32(&mmio_ntb->ep_map);
  5022		partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
  5023		partition_map &= ~(1ULL << partition);
  5024	
  5025		for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
  5026			struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
  5027			u32 table_sz = 0;
  5028			int te;
  5029	
  5030			if (!(partition_map & (1ULL << pp)))
  5031				continue;
  5032	
  5033			pci_dbg(pdev, "Processing partition %d\n", pp);
  5034	
  5035			mmio_peer_ctrl = &mmio_ctrl[pp];
  5036	
  5037			table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
  5038			if (!table_sz) {
  5039				pci_warn(pdev, "Partition %d table_sz 0\n", pp);
  5040				continue;
  5041			}
  5042	
  5043			if (table_sz > 512) {
  5044				pci_warn(pdev,
  5045					 "Invalid Switchtec partition %d table_sz %d\n",
  5046					 pp, table_sz);
  5047				continue;
  5048			}
  5049	
  5050			for (te = 0; te < table_sz; te++) {
  5051				u32 rid_entry;
  5052				u8 devfn;
  5053	
  5054				rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
  5055				devfn = (rid_entry >> 1) & 0xFF;
  5056				pci_dbg(pdev,
  5057					"Aliasing Partition %d Proxy ID %02x.%d\n",
  5058					pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
  5059				pci_add_dma_alias(pdev, devfn);
  5060			}
  5061		}
  5062	
  5063		pci_iounmap(pdev, mmio);
  5064		pci_disable_device(pdev);
  5065	}
  5066	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8531,
  5067				quirk_switchtec_ntb_dma_alias);
  5068	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8532,
  5069				quirk_switchtec_ntb_dma_alias);
  5070	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8533,
  5071				quirk_switchtec_ntb_dma_alias);
  5072	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8534,
  5073				quirk_switchtec_ntb_dma_alias);
  5074	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8535,
  5075				quirk_switchtec_ntb_dma_alias);
  5076	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8536,
  5077				quirk_switchtec_ntb_dma_alias);
  5078	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8543,
  5079				quirk_switchtec_ntb_dma_alias);
  5080	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8544,
  5081				quirk_switchtec_ntb_dma_alias);
  5082	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8545,
  5083				quirk_switchtec_ntb_dma_alias);
  5084	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8546,
  5085				quirk_switchtec_ntb_dma_alias);
  5086	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8551,
  5087				quirk_switchtec_ntb_dma_alias);
  5088	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8552,
  5089				quirk_switchtec_ntb_dma_alias);
  5090	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8553,
  5091				quirk_switchtec_ntb_dma_alias);
  5092	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8554,
  5093				quirk_switchtec_ntb_dma_alias);
  5094	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8555,
  5095				quirk_switchtec_ntb_dma_alias);
  5096	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8556,
  5097				quirk_switchtec_ntb_dma_alias);
  5098	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8561,
  5099				quirk_switchtec_ntb_dma_alias);
  5100	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8562,
  5101				quirk_switchtec_ntb_dma_alias);
  5102	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8563,
  5103				quirk_switchtec_ntb_dma_alias);
  5104	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8564,
  5105				quirk_switchtec_ntb_dma_alias);
  5106	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8565,
  5107				quirk_switchtec_ntb_dma_alias);
  5108	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8566,
  5109				quirk_switchtec_ntb_dma_alias);
  5110	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8571,
  5111				quirk_switchtec_ntb_dma_alias);
  5112	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8572,
  5113				quirk_switchtec_ntb_dma_alias);
  5114	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8573,
  5115				quirk_switchtec_ntb_dma_alias);
  5116	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8574,
  5117				quirk_switchtec_ntb_dma_alias);
  5118	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8575,
  5119				quirk_switchtec_ntb_dma_alias);
  5120	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8576,
  5121				quirk_switchtec_ntb_dma_alias);
  5122	
  5123	/*
  5124	 * The Nvidia GPU on many Intel-based Asus products is unusable after
  5125	 * S3 resume. However, for unknown reasons, rewriting the value of register
  5126	 * 'Prefetchable Base Upper 32 Bits' on the parent PCI bridge works around
  5127	 * the issue.
  5128	 */
  5129	static void quirk_asus_pci_prefetch(struct pci_dev *bridge)
  5130	{
  5131		const char *sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
  5132		u32 value;
  5133	
> 5134		if (strcmp(sys_vendor, "ASUSTeK COMPUTER INC.") != 0)

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Attachment: .config.gz
Description: application/gzip


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