Hey, On 09/08/18 12:51 PM, Eric Pilmore wrote: >>> Was wondering if anybody here has used IOAT DMA engines with an >>> IOMMU turned on (Xeon based system)? My specific question is really >>> whether it is possible to DMA (w/IOAT) to a PCI BAR address as the >>> destination without having to map that address to the IOVA space of >>> the DMA engine first (assuming the IOMMU is on)? I haven't tested this scenario but my guess would be that IOAT would indeed go through the IOMMU and the PCI BAR address would need to be properly mapped into the IOAT's IOVA. The fact that you see DMAR errors is probably a good indication that this is the case. I really don't know why you'd want to DMA something without mapping it. >> So is this a peer-to-peer DMA scenario? You mention DMA, which would >> be a transaction initiated by a PCI device, to a PCI BAR address, so >> it doesn't sound like system memory is involved. > > No, not peer-to-peer. This is from system memory (e.g. SKB buffer which > has had an IOMMU mapping created) to a PCI BAR address. It's definitely peer-to-peer in the case where you are using a DMA engine in the PCI tree. You have the DMA PCI device sending TLPs directly to the PCI BAR device. So, if everything is done right, the TLPs will avoid the root complex completely. (Though, ACS settings could also prevent this from working and you'd either get similar DMAR errors or they'd disappear into a black hole). When using the IOAT, it is part of the CPU so I wouldn't say it's really peer-to-peer. But an argument could be made that it is. Though, this is exactly what the existing ntb_transport is doing: DMAing from system memory to a PCI BAR and vice versa using IOAT. Logan
