From: Catalin Marinas > Sent: 08 August 2018 13:17 ... > I think hazarding is what goes wrong here, especially since with > overlapping unaligned addresses. However, I disagree that it is > impossible to implement this properly on a platform with PCIe so that > Normal NC mappings can be used. I've been trying to follow this discussion... Is the problem just that reads don't snoop/flush the write-combining buffer? Aligned writes that end on an appropriate boundary will leave the write combining buffer empty. But if the buffer isn't emptied the PCIe read gets ahead of the PCIe write. ISTR even x86 requires a fence instruction in some sequence associated with write-combining writes. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
