Hello Russell, On Wed, 1 Aug 2018 10:21:19 +0100, Russell King - ARM Linux wrote: > All PCI devices must treat Configuration Space write operations > to reserved registers as no-ops; that is, the access must be > completed normally on the bus and the data discarded. Read > accesses to reserved or unimplemented registers must be completed > normally and a data value of 0 returned. > > (eg) PCI status: > Reserved bits should be read-only and return zero when read. > A one bit is reset (if it is not read-only) whenever the register > is written, and the write data in the corresponding bit location > is a 1. > > [which is why doing the read-modify-write action that some host > bridges that only support 32-bit accesses is dangerous - it leads > to various status bits being inadvertently reset.] Speaking of this, the generic pci_generic_config_write32() function indeed does this incorrectly, and prints a warning. However, I just looked at the pci-thunder-pem code, and it seems to correctly account for those W1C bits, by having an explicit list of registers and their W1C bits (see thunder_pem_bridge_w1c_bits). This isn't specific to the Thunder PCIe controller at all, and would benefit from being made generic, no ? Best regards, Thomas -- Thomas Petazzoni, CTO, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com
