>-----Original Message----- >From: Mika Westerberg [mailto:mika.westerberg@xxxxxxxxxxxxxxx] >Sent: Thursday, June 21, 2018 2:20 PM >To: Lukas Wunner <lukas@xxxxxxxxx> >Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>; Wysocki, Rafael J <rafael.j.wysocki@xxxxxxxxx>; Raj, Ashok <ashok.raj@xxxxxxxxx>; Busch, >Keith <keith.busch@xxxxxxxxx>; Yinghai Lu <yinghai@xxxxxxxxxx>; Sinan Kaya <okaya@xxxxxxxxxx>; linux-pci@xxxxxxxxxxxxxxx; Greg Kroah- >Hartman <greg@xxxxxxxxx>; Thomas Gleixner <tglx@xxxxxxxxxxxxx>; Patel, Mayurkumar <mayurkumar.patel@xxxxxxxxx>; Kenji Kaneshige ><kaneshige.kenji@xxxxxxxxxxxxxx>; Stefan Roese <sr@xxxxxxx>; Rajat Jain <rajatja@xxxxxxxxxx>; Alex Williamson ><alex.williamson@xxxxxxxxxx>; Andreas Noever <andreas.noever@xxxxxxxxx> >Subject: Re: [PATCH 00/32] Rework pciehp event handling & add runtime PM > >On Sat, Jun 16, 2018 at 09:25:00PM +0200, Lukas Wunner wrote: >> Rework pciehp to use modern, threaded IRQ handling. The slot is powered >> on and off synchronously in the IRQ thread, no indirection via a work >> queue anymore. >> >> When the slot is enabled/disabled by the user via sysfs or an Attention >> Button press, a request is sent to the IRQ thread. The IRQ thread is >> thus the sole entity enabling/disabling the slot. >> >> The IRQ thread can cope with missed events, e.g. if a card is inserted >> and immediately pulled out before the IRQ thread had a chance to react. >> It also tolerates an initially unstable link as observed in the wild by >> Stefan Roese. >> >> Finally, runtime PM support is added. This was the original motivation >> of the series because runtime suspending hotplug ports is needed to power >> down Thunderbolt controllers on idle, which saves ~1.5W per controller. >> Runtime resuming ports takes tenths of milliseconds during which events >> may be missed, this in turn necessitated the event handling rework. >> >> I've pushed the series to GitHub to ease reviewing/fetching: >> https://github.com/l1k/linux/commits/pciehp_runpm_v2 >> >> Please review and test. > >I've tested this series on every native PCIe hotplug system I have here, >including one non-Thunderbolt (just hotplugging NVMes) and I did not >observe any issues. There are few minor comments for few patches but in >general this is really nice cleanup. I have not found any issues with this test series on my test setup related to PCIe hotplug. Intel Deutschland GmbH Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Christian Lamprechter Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928
