Am 10.05.2018 um 16:20 schrieb Stephen Bates:
Hi Jerome
As it is tie to PASID this is done using IOMMU so looks for caller
of amd_iommu_bind_pasid() or intel_svm_bind_mm() in GPU the existing
user is the AMD GPU driver see:
Ah thanks. This cleared things up for me. A quick search shows there are still no users of intel_svm_bind_mm() but I see the AMD version used in that GPU driver.
Just FYI: There is also another effort ongoing to give both the AMD,
Intel as well as ARM IOMMUs a common interface so that drivers can use
whatever the platform offers fro SVM support.
One thing I could not grok from the code how the GPU driver indicates which DMA events require ATS translations and which do not. I am assuming the driver implements someway of indicating that and its not just a global ON or OFF for all DMAs? The reason I ask is that I looking at if NVMe was to support ATS what would need to be added in the NVMe spec above and beyond what we have in PCI ATS to support efficient use of ATS (for example would we need a flag in the submission queue entries to indicate a particular IO's SGL/PRP should undergo ATS).
Oh, well that is complicated at best.
On very old hardware it wasn't a window, but instead you had to use
special commands in your shader which indicated that you want to use an
ATS transaction instead of a normal PCIe transaction for your
read/write/atomic.
As Jerome explained on most hardware we have a window inside the
internal GPU address space which when accessed issues a ATS transaction
with a configurable PASID.
But on very newer hardware that window became a bit in the GPUVM page
tables, so in theory we now can control it on a 4K granularity basis for
the internal 48bit GPU address space.
Christian.
Cheers
Stephen
