On 4/20/2018 11:04 AM, Alex Williamson wrote: > Is there a concern here about whether the endpoint device driver or the > PCI core really knows better about link retraining? This makes me > remember my unfinished (and need to revisit) Pericom quirk[1] where > errata in the PCIe switch requires that upstream and downstream links > are balanced (ie. same link rate) or else enabling ACS results in > packets not properly flowing through the switch. If an endpoint driver > starts deciding to retrain links, overriding quirks in the PCI core, > then such topology manipulation isn't possible. Why does the > driver .probe() function think it can retrain at a higher link rate > than PCI core? Thanks, The example given is for some serdes firmware load to happen in probe and then performing a retrain to reach to a better speed. It becomes a chicken and egg problem. 1. Endpoint HW trains to gen1 by default pre-boot. 2. PCI core enumerates the device. 3. Endpoint driver gets loaded 4. Driver does the firmware programming followed by a link retrain. I think it is the responsibility of the PCI core to provide reset APIs. However, expecting endpoint drivers to be knowledgeable about hotplug is too much. We can certainly contain AER change into pci directory by moving the slot reset function to drivers/pci.h file. But, we need to think about what to do about VFIO and other endpoint initiated reset cases. My suggestion was to move this into a single API and remove all other APIs from include/linux/pci.h. Coming back to this patch... Do we need a retrain API with the speed that driver wants to reach to? API can return what was actually accomplished. The quirk from Alex can run inside this API to make a decision on what speed do we actually want to reach to for a given PCI topology by reprogramming the target link speed field. -- Sinan Kaya Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
