On Tue, Feb 27, 2018 at 12:59:05PM +0100, Niklas Cassel wrote: > A 64-bit BAR uses the succeeding BAR for the upper bits, therefore > we cannot call pci_epc_set_bar() on a BAR that follows a 64-bit BAR. > > If pci_epc_set_bar() is called with flag PCI_BASE_ADDRESS_MEM_TYPE_64, PCI_BASE_ADDRESS_MEM_TYPE_64 is detected through a sizeof(dma_addr_t). I thought we decided to describe the BARs not as dma_addr_t + size but as resources, which would allow you to have flags describing their actual size. Current code has a fixed BAR size defined by the dma_addr_t type size and I do not think that's what we really want. How is (in HW I mean) actually the BAR size configured in a given EPF ? Thanks, Lorenzo > it has to be up to the controller driver to write both BAR[x] and BAR[x+1] > (and BAR_mask[x] and BAR_mask[x+1]). > > Signed-off-by: Niklas Cassel <niklas.cassel@xxxxxxxx> > --- > drivers/pci/endpoint/functions/pci-epf-test.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c > index 64d8a17f8094..ecbf6a7750dc 100644 > --- a/drivers/pci/endpoint/functions/pci-epf-test.c > +++ b/drivers/pci/endpoint/functions/pci-epf-test.c > @@ -382,6 +382,8 @@ static int pci_epf_test_set_bar(struct pci_epf *epf) > if (bar == test_reg_bar) > return ret; > } > + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) > + bar++; > } > > return 0; > -- > 2.14.2 >
