On Wed, Feb 7, 2018 at 9:02 AM, Ran Shalit <ranshalit@xxxxxxxxx> wrote: > On Wed, Feb 7, 2018 at 8:12 AM, Ravikiran Gummaluri <rgummal@xxxxxxxxxx> wrote: >> I am assuming DMA as on Host side. In this case Host DMA will me master for all transactions(Tx or Rx). >> Point 4 may be not relevant ,as DMA on host is responsible in RX also. >> All this points will be relevant when DMA is working on memory mapped mode meaning transferring from Host memory to EP memory. >> In a simple example , Tx direction DMA descriptors will be programmed with Host buffer and BAR address. Host will program DMA register to trigger transfer. DMA on host will move Data from Host to EP. >> IN RX direction , DMA will be preprogrammed with host buffers, Host will program DMA registers to fetch data from EP to Host. >> > Is it required to memory map dma bufferis in host even if dma is in device ? Is it that examples such as pci-skeleton.c assume DMA is in device , and yet requires dma mapping ? Regards, Ran > I tried to check pci-skeleton.c as an example: > It allocates dma buffer in host, but triggering dma is done by writing > a register in EP memory (as if the endpoint is actually triggering the > dma transaction), so I'm a bit confused here. I think that it triggers > both tx and rx the same way (writing EP memory register). > Are you familiar with a simple example or tuturial which explains how > to operate host dma in PCI ? I am a bit confused with this topic of > dma in pci. > > Thank you, > Ran > > > > Thanks, > Ran > > > >>> -----Original Message----- >>> From: linux-pci-owner@xxxxxxxxxxxxxxx [mailto:linux-pci- >>> owner@xxxxxxxxxxxxxxx] On Behalf Of Ran Shalit >>> Sent: Wednesday, February 7, 2018 12:33 AM >>> To: linux-pci@xxxxxxxxxxxxxxx >>> Subject: understanding DMA in PCI drivers >>> >>> Hello, >>> >>> I write a pci linux driver, and after reviewing some examples in kernel, there >>> is issue I am not sure about: >>> DMA seems to follow the following steps in PCI: >>> 1. driver allocate dma buffers and map them to BAR. >>> 2. driver initialize device to be familiar with dma addresses. >>> 3. tx from cpu to device: driver trigger dma, by writing into device BARs. >>> 4. rx from device to cpu: device is responsible for triggering DMA (driver does >>> not do anything here) 5. tx/rx completion: interrupt from DMA (in cpu) 6. >>> interrupt handler of section 5 above checks that device finished tx/rx. >>> >>> Is the above understanding correct ? >>> 1. As to 6, I am not sure about, is it that device knows that transaction is >>> finished (DMA is in soc , not device) ? >>> 2. How does device triggers DMA from device to cpu, is it by simply writing to >>> BAR ? >>> 3. How does device triggers DMA from cpu to device, is it by simply reading >>> from BAR ? >>> >>> Thank you, >>> Ran
