On Thu, Jan 25, 2018 at 02:15:21PM -0700, Keith Busch wrote: > On Thu, Jan 25, 2018 at 01:55:12PM -0600, Bjorn Helgaas wrote: > > > After we clear PCI_EXP_DPC_STATUS_TRIGGER, we're supposed to "honor > > timing requirements ... with respect to the first Configuration Read > > following a Conventional Reset" (PCIe r4.0, sec 7.9.15.4). Where does > > that happen? > > That is referring to reading the downstream port, and that is not > handled by the DPC driver. The expectation is that the link is down on a > DPC event, and the Link Up is handled by the pciehp driver, which > should be honoring those timing requirements. Sorry, I didn't mean "reading the downstream port". You can config read that anytime. I meant issuing a config read to the device connected downstream the contained port.
