On 2018-01-09 14:48, Niklas Cassel wrote:
<snip>
/* setup bus numbers */
val = dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS);
val &= 0xff000000;
- val |= 0x00010100;
+ val |= 0x00ff0100;
dw_pcie_writel_rc(pp, PCI_PRIMARY_BUS, val);
/* setup command register */
Above version logically fixes it for all dwc devices using a bridge after the RC, not only imx6.
If this is fine, I would submit the patch above and drop the current one.
I can confirm that commit a20c7f36bd3d ("PCI: Do not allocate more buses than
available in parent") broke enumerating PCIe devices behind a PCIe switch
on ARTPEC-6 (which uses the DWC IP).
(FTR, arch/arm/boot/dts/artpec6.dtsi specifies bus-range = <0x00 0xff>).
This patch resolves the problem.
(I verified on linux-next: next-20180109).
However, note that I had to patch the file
drivers/pci/dwc/pcie-designware-host.c
rather than
drivers/pci/host/pcie-designware.c,
which this patch suggests.
Above internally used example patch is based on kernel 4.9.74, where
this file hasn't moved/renamed yet to dwc subfolder
I'll post a proper one shortly for the upstream tree.
Thanks for testing,
Koen
Please feel free to submit a new patch with:
Tested-by: Niklas Cassel <niklas.cassel@xxxxxxxx>
