On Tue, Sep 19, 2017 at 04:43:18PM +0200, Gregory CLEMENT wrote: > Hi Jan, > > On lun., août 28 2017, Jan Luebbe <jlu@xxxxxxxxxxxxxx> wrote: > > > At least the Armada XP SoC supports 4GB on a single DRAM window. Because > > the size register values contain the actual size - 1, the MSB is set in > > that case. For example, the SDRAM window's control register's value is > > 0xffffffe1 for 4GB (bits 31 to 24 contain the size). > > > > The MBUS driver reads back each window's size from registers and > > calculates the actual size as (control_reg | ~DDR_SIZE_MASK) + 1, which > > overflows for 32 bit values, resulting in other miscalculations further > > on (a bad RAM window for the CESA crypto engine calculated by > > mvebu_mbus_setup_cpu_target_nooverlap() in my case). > > > > This patch changes the type in 'struct mbus_dram_window' from u32 to > > u64, which allows us to keep using the same register calculation code in > > most MBUS-using drivers (which calculate ->size - 1 again). > > > > Your patch looks good, but as it is a fix we should also apply it on > stable, could you provide the commit to fix? It was there just from the start: the .c file was introduced in v3.10-rc1~64^2~1^2~8^2~2 and already did that 32 bit calculus. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ |
