Both iproc and xgene mask out PCI_EXP_RTCAP_CRSVIS (CRS Software
Visibility). The point of these is to make them do it more
consistently.
For iproc, I renamed PCI_EXP_CAP to IPROC_PCI_EXP_CAP to make it
obviously iproc-specific. Apparently the X-Gene PCIe capability is at
0x40, at least for V1 root ports, so I added a corresponding
XGENE_V1_PCI_EXP_CAP.
X-Gene also defines PCIECORE_CTLANDSTATUS at 0x50, which is looks a
little like the PCI_EXP_LNKCTL and PCI_EXP_LNKSTA registers which
would be at 0x50 in the PCIe capability, and PCIECORE_CTLANDSTATUS is
used to determine whether the link is up. If this *were* actually
part of a PCIe capability, I'd like to use the generic definitions.
But it's not clear from the code because PCIECORE_CTLANDSTATUS is used
with a simple xgene_pcie_readl(), while we read PCI_EXP_RTCTL using
pci_generic_config_read32(), so I'm not sure they're in the same
address space. So I didn't touch anything there.
Also, some trivial whitespace cleanup.
---
Bjorn Helgaas (4):
PCI: iproc: Rename PCI_EXP_CAP to IPROC_PCI_EXP_CAP
PCI: iproc: Clean up whitespace
PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset
PCI: xgene: Clean up whitespace
drivers/pci/host/pci-xgene.c | 41 +++----
drivers/pci/host/pcie-iproc.c | 250 ++++++++++++++++++++---------------------
2 files changed, 144 insertions(+), 147 deletions(-)
