The DWC PCIe host controller doesn't support MSI and legacy IRQs at the same time. If the MSI controller is in use (which is always the case, as PCIe port serives are using MSI IRQs when available), legacy endpoint devices are unable to raise an IRQ. Remove the MSI irq line to inhibit the MSI controller from being used, which is a much better default, as most enpoint devices are able to fall back to legacy PCIe IRQs, if MSI are not available. Systems which are validated to work in MSI only mode can opt-in to use the MSI controller by adding back the MSI irq line in the board DT. Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> --- arch/arm/boot/dts/imx6qdl.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index a9723b94bafa..0f47a9d4024e 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -209,8 +209,6 @@ ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, -- 2.11.0
