+ Adding Bjorn
Sorry for top post, we are looking to pull this into the latest REL7.4
release. Would like
the maintainer to take a look. Thanks
On Tue, Aug 1, 2017 at 4:15 PM, Alex Williamson
<alex.williamson@xxxxxxxxxx> wrote:
> On Tue, 1 Aug 2017 16:08:13 -0700
> Feng Kan <fkan@xxxxxxx> wrote:
>
>> The APM X-Gene PCIe root port does not support ACS at this point.
>> However, the hw provides isolation and source validation through
>> the SMMU. The stream ID generated by the PCIe ports contain both
>> the BDF as well as the port ID in its 3 most significant bits.
>> Turn on ACS but disable all the peer to peer features.
>>
>> Signed-off-by: Feng Kan <fkan@xxxxxxx>
>> ---
>> V4 Change: Remove TB & TD flags from ACS mask
>> V3 Change: Add comment regarding unique port id in stream ID
>> V2 Change: Move XGene ACS quirk to unique XGene function
>>
>> drivers/pci/quirks.c | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>
>
> Reviewed-by: Alex Williamson <alex.williamson@xxxxxxxxxx>
>
>
>> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
>> index 085fb78..22343b3 100644
>> --- a/drivers/pci/quirks.c
>> +++ b/drivers/pci/quirks.c
>> @@ -4120,6 +4120,18 @@ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
>> return acs_flags ? 0 : 1;
>> }
>>
>> +static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
>> +{
>> + /*
>> + * XGene root matching this quirk do not allow peer-to-peer
>> + * transactions with others, allowing masking out these bits as if they
>> + * were unimplemented in the ACS capability.
>> + */
>> + acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
>> +
>> + return acs_flags ? 0 : 1;
>> +}
>> +
>> /*
>> * Many Intel PCH root ports do provide ACS-like features to disable peer
>> * transactions and validate bus numbers in requests, but do not provide an
>> @@ -4368,6 +4380,8 @@ static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
>> { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
>> /* Cavium ThunderX */
>> { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
>> + /* APM XGene */
>> + { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
>> { 0 }
>> };
>>
>
