On 06/05/2017 06:19 PM, Joao Pinto wrote:
> The Synopsys PCIe Controller supports up to 256 IRQs distributed
> by 8 controller registers.
>
> Having this in mind, the number of the maximum number of
> IRQs was changed to 256 and now the number of controllers is
> calculated based on the number of vectors used by the specific
> SoC driver.
>
> Signed-off-by: Joao Pinto <jpinto@xxxxxxxxxxxx>
> ---
> Change v1->v2:
> - New patch
>
> drivers/pci/dwc/pcie-designware-host.c | 12 ++++++++----
> drivers/pci/dwc/pcie-designware.h | 10 +++-------
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
> index 6c771cc..31c7ccd 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++ b/drivers/pci/dwc/pcie-designware-host.c
> @@ -73,11 +73,13 @@ static struct msi_domain_info dw_pcie_msi_domain_info = {
> /* MSI int handler */
> irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
> {
> - u32 val;
> int i, pos, irq;
> + u32 val, num_ctrls;
> irqreturn_t ret = IRQ_NONE;
>
> - for (i = 0; i < MAX_MSI_CTRLS; i++) {
> + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> +
> + for (i = 0; i < num_ctrls; i++) {
> dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
> &val);
Hello Joao
Nice to see that we now have support for all 8 controllers,
good job!
Older versions of the DesignWare IP only had support for a
combined msi irq (msi_ctrl_int), but since recent versions
of the IP also supports a dedicated irq line per controller
(msi_ctrl_int_vec[7:0]), do you think that it makes sense
to take this into consideration for this patchset?
By doing so, dw_handle_msi_irq would not have to iterate
over all 8 controllers, as the irq itself would tell us
what controller to read the status from (to finally see
which irq(s) that actually triggered).
Regards,
Niklas
