> The IRQ domain for INTX interrupts has 4 entries, numbered 0 to 3. This matches
> what the hardware reports from the interrupt FIFO exactly, but
> xilinx_pcie_intr_handler was adding 1 to that value to convert to the range 1 to
> 4. Stop adding 1, such that all of INTA through to INTD fall within the range of
> the IRQ domain.
>
Paul, this change is not required.
hwirq for legacy domain is being assigned by kernel PCIe subsystem based on PCI_INTERRUPT_PIN, which as per
protocol starts from 1 and not zero, due to this 1 is being added.
Regards,
Bharat
> Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx>
> Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver")
> Cc: Bharat Kumar Gogada <bharatku@xxxxxxxxxx>
> Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
> Cc: Michal Simek <michal.simek@xxxxxxxxxx>
> Cc: Ravikiran Gummaluri <rgummal@xxxxxxxxxx>
> Cc: linux-pci@xxxxxxxxxxxxxxx
>
> ---
>
> Changes in v4: None
>
> Changes in v3:
> - Split out from Boston patchset.
>
> Changes in v2:
> - Add Fixes tag.
>
> drivers/pci/host/pcie-xilinx.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index
> 2fe2df51f9f8..6be2e5ee44f1 100644
> --- a/drivers/pci/host/pcie-xilinx.c
> +++ b/drivers/pci/host/pcie-xilinx.c
> @@ -440,8 +440,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void
> *data)
> XILINX_PCIE_REG_RPIFR1);
>
> /* Handle INTx Interrupt */
> - val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
> - XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
> + val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
> + XILINX_PCIE_RPIFR1_INTR_SHIFT;
> generic_handle_irq(irq_find_mapping(port-
> >leg_domain,
> val));
> }
> --
> 2.13.0
