[Q] What about PCI mmio access alignment?

["Du, Changbin" <changbin.du@xxxxxxxxx>]

Hi, guys,
I have a basic quesion about the alignment when access PCI bar mmio space. Is
the address accessed must be DW aligned and count must be DW aligned?

As far as I know, The address field of TLB ignore lower 2 bits and the unit of
length field also is DW. So does it mean above question is Yes? Else will CPU
handle unaligned access for mmio space?

I want to know wether below access illegal or not:
  - readb(bar0)
  - readb(bar0 + 1)
  - readl(bar0)

Thanks,
Changbin Du

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