On Mon, May 08, 2017 at 10:54:55AM +0200, Christian König wrote: > Am 05.05.2017 um 01:04 schrieb Bjorn Helgaas: > >I *think* this will be broken by the current implementation of > >Christian's patch to enable a 64-bit host bridge window: > > > > https://lkml.kernel.org/r/1493890270-1188-5-git-send-email-deathsimple@xxxxxxxxxxx > > > >because pci_register_host_bridge() runs before we scan the bus, and > >Christian's patch adds a quirk that runs when we enumerate the AMD > >host bridge device. > > > >If we apply this and Christian's patch, I think we could end up with > >a host bridge window above 4G, but with bridge->has_mem64 not set. > Yes, indeed. I can adjust my patch, but I would prefer not to do so. > > I don't completely understand the background of this change, but > from what I know how the BIOS (at least on X86) allocates resources > it doesn't sounds correct to me. > > Maybe we just need a Sparc specific quirk here instead of changing > the common logic? There's nothing in Yinghai's patch that's conceptually Sparc-specific, so I would prefer not to artificially tie it to Sparc. One possibility would be to compute has_mem64 when we need it instead of caching it.
