On Sat, Apr 8, 2017 at 10:06 PM, Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote: > On Sat, Apr 08, 2017 at 07:00:19PM +0200, David Woodhouse wrote: >> ... >> I note it's also reading PCI_CACHE_LINE_SIZE From config space for each >> device in pci_apply_final_quirks(). How long does that take? > > I don't know, but it's pointless on modern PCIe systems where the > Cache Line Size has no effect. It'd be really nice if somebody > cleaned that up and got rid of the read itself and the useless > messages. What I can think of is 10ms delay for PM. The laptop might be one of Intel BayTrails where we have it. But it's just a guess. -- With Best Regards, Andy Shevchenko
