On Wednesday, April 26, 2017 6:54 AM, Dongdong Liu wrote; > > Tested-by: Dongdong Liu <liudongdong3@xxxxxxxxxx> > > I tested the patchset on HiSilicon ARM64 D05 board.It works ok with 82599 > netcard. Thank you for testing these patches. HiSilicon PCIe may use Designware-based PCIe controller. In my opinion, other Designware-based PCIe controller will work properly. To Dongdong Liu, Khuong Dinh, and other people, If possible, can you check the output of 'lspci -v'? If you find something different, please share it with us. Good luck. Best regards, Jingoo Han > > Thanks, > Dongdong > 在 2017/4/25 14:40, Jon Masters 写道: > > On 04/19/2017 12:48 PM, Lorenzo Pieralisi wrote: > > > >> On some platforms (ie ARM/ARM64) ioremap fails to comply with the PCI > >> configuration non-posted write transactions requirement, because it > >> provides a memory mapping that issues "bufferable" or, in PCI terms > >> "posted" write transactions. Likewise, the current pci_remap_iospace() > >> implementation maps the physical address range that the PCI translates > >> to I/O space cycles to virtual address space through pgprot_device() > >> attributes that on eg ARM64 provides a memory mapping issuing > >> posted writes transactions, which is not PCI specifications compliant. > > > > Side note that I've pinged all of the ARM server vendors and asked them > > to verify this patch series on their platforms. > > > > Jon. > > > > . > >
