[PATCH 6/9] lspci: Decode "Slot Implemented" for PCI/PCI-X to PCIe Bridges

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From: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>

The secondary side of a PCI/PCI-X to PCIe Bridge (a "reverse bridge") is a
PCIe Downstream Port and could support a slot just like Root Ports and
Switch Downstream Ports.

Decode "Slot Implemented" for reverse bridges and, if true, the Slot
Capabilities, Control, and Status registers.

For a reverse bridge with no slot, the difference in the "lspci -vv" output
looks like this:

-    Capabilities: [40] Express (v2) PCI/PCI-X to PCI-Express Bridge, MSI 00
+    Capabilities: [40] Express (v2) PCI/PCI-X to PCI-Express Bridge (Slot-), MSI 00

Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
---
 ls-caps.c              |    4 +
 tests/cap-exp-rev-slot |  288 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 291 insertions(+), 1 deletion(-)
 create mode 100644 tests/cap-exp-rev-slot

diff --git a/ls-caps.c b/ls-caps.c
index 1230746..2d3b59d 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -1159,7 +1159,9 @@ cap_express(struct device *d, int where, int cap)
       printf("PCI-Express to PCI/PCI-X Bridge");
       break;
     case PCI_EXP_TYPE_PCIE_BRIDGE:
-      printf("PCI/PCI-X to PCI-Express Bridge");
+      slot = cap & PCI_EXP_FLAGS_SLOT;
+      printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
+	     FLAG(cap, PCI_EXP_FLAGS_SLOT));
       break;
     case PCI_EXP_TYPE_ROOT_INT_EP:
       link = 0;
diff --git a/tests/cap-exp-rev-slot b/tests/cap-exp-rev-slot
new file mode 100644
index 0000000..737d963
--- /dev/null
+++ b/tests/cap-exp-rev-slot
@@ -0,0 +1,288 @@
+01:0a.0 PCI bridge: Broadcom Corporation Device 9039 (prog-if 00 [Normal decode])
+	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+	Latency: 0, Cache Line Size: 64 bytes
+	Region 0: Memory at 4001200000 (64-bit, prefetchable)
+	Bus: primary=01, secondary=02, subordinate=03, sec-latency=0
+	I/O behind bridge: None
+	Memory behind bridge: None
+	Prefetchable memory behind bridge: None
+	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
+	BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
+		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+	Capabilities: [40] Express (v2) PCI/PCI-X to PCI-Express Bridge (Slot-), MSI 00
+		DevCap:	MaxPayload 128 bytes, PhantFunc 0
+			ExtTag- RBE-
+		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+			MaxPayload 128 bytes, MaxReadReq 4096 bytes
+		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+		LnkCap:	Port #0, Speed unknown, Width x0, ASPM not supported, Exit Latency L0s <64ns, L1 <1us
+			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
+		LnkCtl:	ASPM Disabled; Disabled- CommClk-
+			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+		LnkSta:	Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
+		DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
+		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
+			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+			 Compliance De-emphasis: -6dB
+		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+	Capabilities: [90] Vendor Specific Information: Len=70 <?>
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