On Fri, Apr 07, 2017 at 02:59:17PM +0800, Shawn Lin wrote: > All platforms using Rockchip use a common clock for the Root > Port and the slot connected to it. Indicate this by setting > the Slot Clock Configuration (PCI_EXP_LNKSTA_SLC) bit in the > Root Port's Link Status. > > Per the Implementation Note in the spec (PCIe r3.1, sec 7.8.7), > if the downstream component also sets PCI_EXP_LNKSTA_SLC, software > may set the Common Clock Configuration (PCI_EXP_LNKCTL_CCC) bits on > both ends of the Link. This is done by pcie_aspm_configure_common_clock() > > Cc: Brian Norris <briannorris@xxxxxxxxxxxx> > Cc: jeffy.chen <jeffy.chen@xxxxxxxxxxxxxx> > Signed-off-by: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx> Applied to pci/host-rockchip for v4.12, thanks! > --- > > Changes in v2: > - replace CCC with SLC > - reword the commit msg > > drivers/pci/host/pcie-rockchip.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c > index 26ddd35..7e7a6b6 100644 > --- a/drivers/pci/host/pcie-rockchip.c > +++ b/drivers/pci/host/pcie-rockchip.c > @@ -596,7 +596,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > > /* Set RC's clock architecture as common clock */ > status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); > - status |= PCI_EXP_LNKCTL_CCC; > + status |= PCI_EXP_LNKSTA_SLC << 16; > rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); > > /* Enable Gen1 training */ > -- > 1.9.1 > >
