On Sun, Mar 12, 2017 at 11:23 PM, Linus Walleij <linus.walleij@xxxxxxxxxx> wrote: > This adds device tree bindings for the Faraday technology PCI > Host Bridge. This IP is found in the Storlink/Storm/Cortina > Gemini SoC platform. > > Cc: Janos Laube <janos.dev@xxxxxxxxx> > Cc: Paulius Zaleckas <paulius.zaleckas@xxxxxxxxx> > Cc: Hans Ulli Kroll <ulli.kroll@xxxxxxxxxxxxxx> > Cc: Florian Fainelli <f.fainelli@xxxxxxxxx> > Cc: devicetree@xxxxxxxxxxxxxxx > Cc: Feng-Hsin Chiang <john453@xxxxxxxxxxxxxxxx> > Cc: Greentime Hu <green.hu@xxxxxxxxx> > Acked-by: Rob Herring <robh@xxxxxxxxxx> > Signed-off-by: Linus Walleij <linus.walleij@xxxxxxxxxx> > --- > ChangeLog v4->v5: > - No changes, just resend as everything else is rebased onto > v4.11-rc1. Bjorn do you have any further comments or can we queue patch 1+2 of this series? I want to submit the DTS patches to the ARM SoC tree, so I need to be sure the bindings+driver are merge material first. Yours, Linus Walleij
