Hi Russell, On Mon, Mar 20, 2017 at 04:43:55PM +0000, Russell King - ARM Linux wrote: > On Mon, Feb 27, 2017 at 03:14:16PM +0000, Lorenzo Pieralisi wrote: > > The PCI bus specifications (rev 3.0, 3.2.5 "Transaction Ordering > > and Posting") define rules for PCI configuration space transactions > > ordering and posting, that state that configuration writes have to > > be non-posted transactions. > > > > Current ioremap interface on ARM provides mapping functions that > > provide "bufferable" writes transactions (ie ioremap uses MT_DEVICE > > memory type) aka posted writes, so PCI host controller drivers have > > no arch interface to remap PCI configuration space with memory > > attributes that comply with the PCI specifications for configuration > > space. > > > > Implement an ARM specific pci_remap_cfgspace() interface that allows to > > map PCI config memory regions with MT_UNCACHED memory type (ie strongly > > ordered - non-posted writes), providing a remap function that complies > > with PCI specifications for config space transactions. > > Doesn't this have the side effect that configuration writes can bypass > writes to device memory if there isn't an intervening dsb? (They > probably can do on some CPUs today anyway.) I assumed that in plain terms, the difference between MT_DEVICE and MT_UNCACHED is write posting (aka bufferable) behaviour (across CPU architecture versions) and that does not affect write ordering rules. You and Catalin have more insights into ARM 32-bit memory types so I definitely need your input here to be comprehensive and avoid pitfalls, let me know if you have some specific CPUs in mind on which this may trigger a regression. > So, in any case, this looks like an improvement: > > Acked-by: Russell King <rmk+kernel@xxxxxxxxxxxxxxx> Thank you ! Lorenzo
