lspci traces CCC to see if the end-2-end supports common clock, so the current code should work as we mark the CCC bit of RC. However, ASPM code actually check SLC bit of RC and try to compare it with the downstream components' SLC instead. So when enabling ASPM, CCC will be cleared after failing to match SLC with the corresponding bit of downstream components. On one hand, from the code of pcie_aspm_configure_common_clock, we could find that what we actually need to set is SLC. On the other hand, we should also guarantee that CCC should be marked w/o supporting ASPM. This patch fixes this issue. Cc: Brian Norris <briannorris@xxxxxxxxxxxx> Cc: jeffy.chen <jeffy.chen@xxxxxxxxxxxxxx> Signed-off-by: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx> --- drivers/pci/host/pcie-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 26ddd35..7cd4d5c 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -596,7 +596,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) /* Set RC's clock architecture as common clock */ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); - status |= PCI_EXP_LNKCTL_CCC; + status |= (PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKSTA_SLC << 16); rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); /* Enable Gen1 training */ -- 1.9.1
