Hi Bjorn and all I have a question regarding bus addresses for IO resources in the ACPI table. The question is if from an ACPI perspective it is legal to have two entries in separate _CRS methods using the same IO bus address. As an example please see the code at the bottom: we have the same bus address starting at 0x0 with (obviously) different offsets leading to different CPU physical addresses. Is this legal? p.s. full DSDT is here: https://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git/tree/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl?h=estuary-rp Many thanks Gab ---- Device (PCI0) { Name (_HID, "HISI0080") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 0) // Segment of this Root complex Name(_BBN, 0) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources [...] QWordIO ( ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address 0xb7ff0000, // Translate 0x10000 // Length ) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) // PCIe Root bus Device (PCI1) { Name (_HID, "HISI0080") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 1) // Segment of this Root complex Name(_BBN, 0xe0) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources [...] QWordIO ( ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address 0xbdff0000, // Translate 0x10000 // Length ) }) // Name(RBUF) Return (RBUF) } // Method(_CRS)