Hi Joao,
On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>> Add endpoint mode support to designware driver. This uses the
>> EP Core layer introduced recently to add endpoint mode support.
>> *Any* function driver can now use this designware device
>> in order to achieve the EP functionality.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx>
>> ---
>> drivers/pci/dwc/Kconfig | 5 +
>> drivers/pci/dwc/Makefile | 1 +
>> drivers/pci/dwc/pcie-designware-ep.c | 342 ++++++++++++++++++++++++++++++++++
>> drivers/pci/dwc/pcie-designware.c | 51 +++++
>> drivers/pci/dwc/pcie-designware.h | 72 +++++++
>> 5 files changed, 471 insertions(+)
>> create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
>>
<snip>
>> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
>> index 686945d..49b28c8 100644
>> --- a/drivers/pci/dwc/pcie-designware.c
>> +++ b/drivers/pci/dwc/pcie-designware.c
>> @@ -173,6 +173,57 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
>> dev_err(pci->dev, "iATU is not being enabled\n");
>> }
>>
>> +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
>> + u64 cpu_addr, enum dw_pcie_as_type as_type)
>> +{
>> + int type;
>> + void __iomem *base = pci->dbi_base;
>> +
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
>> + PCIE_ATU_REGION_INBOUND | index);
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
>> + lower_32_bits(cpu_addr));
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
>> + upper_32_bits(cpu_addr));
>> +
>> + switch (as_type) {
>> + case DW_PCIE_AS_MEM:
>> + type = PCIE_ATU_TYPE_MEM;
>> + break;
>> + case DW_PCIE_AS_IO:
>> + type = PCIE_ATU_TYPE_IO;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, PCIE_ATU_ENABLE |
>> + PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
>> + return 0;
>> +}
>> +
>
> This Atu programming is for PCI Cores <= 4.70. Please follow the same approach as:
> https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/tree/drivers/pci/dwc/pcie-designware.c?h=pci/host-designware#n95
Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
Thanks
Kishon
