On Fri, Mar 03 2017 at 8:04:07 pm GMT, Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
> On Fri, Mar 03, 2017 at 06:18:02PM +0100, Mason wrote:
>> In fact, I thought I could ignore that BAR, but it is apparently NOT
>> the case, as MSIs are supposed to be sent *within* the BAR of the root.
>
> I don't know much about this piece of the MSI puzzle, but maybe Marc
> can enlighten us. If this Root Port is the target of MSIs and the
> Root Port turns them into some sort of interrupt on the CPU side, I
> can see how this might make sense.
There is a whole range of PCIe RC that require to be programmed with the
doorbell address. It can be any address, but the kernel has to make sure
it is not something you will ever DMA to, as the RC is unlikely to
forward the transaction after having matched it.
> I think it's unusual for the PCI core to assign the MSI target using a
> BAR, though. I think this means you'll have to implement your
> arch_setup_msi_irq() or .irq_compose_msi_msg() method such that it
> looks up that BAR value, since you won't know it at build-time.
A common trick is to set the doorbell address to a well known value,
such as the base address for the PCIe RC itself. Of course, that only
works if the RC doesn't forward writes to the doorbell. Otherwise, any
RAM address will do, provided that it is not something we'd expect to
DMA to.
Thanks,
M.
--
Jazz is not dead, it just smell funny.
