On Mon, Feb 06, 2017 at 10:35:28PM +0100, Lukas Wunner wrote: > On Mon, Feb 06, 2017 at 12:37:06PM +0200, Mika Westerberg wrote: > > On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > > > @Mika, Rafael: Are you aware of Skylake machines with unreliable link > > > training, or perhaps errata of Skylake chips related to link training > > > on hotplug ports? > > > > According to the 100-series (the chipset used with Skylake) errata > > below, I don't see any mentions related to PCIe link training issues. > > > > http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/100-series-chipset-spec-update.pdf > > Yinghai Lu responded off-list that the hardware in question is an > unreleased / secret Intel product, so this particular issue cannot > be expected to be documented publicly at this point. > > Of course this raises the question whether issues with unreleased > products can at all be considered valid regressions, given that the > final product may not regress. It seems like a novelty to me that > patches would get reverted for something like this, but we'll see. I assume the hardware will eventually be released, and I assume the hardware will not be changed because of this issue. I would like to avoid the situation of having v4.9 but not v4.10 work on this hardware.
