On Fri, Jan 20, 2017 at 04:58:37PM +0100, Lucas Stach wrote:
> This causes CPU hangs when the system is reset by the watchdog, as
> the GPRs aren't cleared, but the clocks are back to disabled state.
>
> If the bootloader uses PCIe, it must take care to bring it down
> into a safe state, before passing control to the Linux kernel.
> This is the only way to get a properly operating system at all
> times and circumstances.
>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
Applied to pci/host-imx6 for v4.11, thanks!
I don't really like the idea that we depend on a particular state from the
bootloader, but if there's no way around it, maybe this is the best we can
do.
> ---
> drivers/pci/host/pci-imx6.c | 30 ------------------------------
> 1 file changed, 30 deletions(-)
>
> diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
> index c8cefb078218..42c1987ffb3d 100644
> --- a/drivers/pci/host/pci-imx6.c
> +++ b/drivers/pci/host/pci-imx6.c
> @@ -247,9 +247,6 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
>
> static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
> {
> - struct pcie_port *pp = &imx6_pcie->pp;
> - u32 val, gpr1, gpr12;
> -
> switch (imx6_pcie->variant) {
> case IMX6SX:
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> @@ -266,33 +263,6 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
> IMX6Q_GPR1_PCIE_SW_RST);
> break;
> case IMX6Q:
> - /*
> - * If the bootloader already enabled the link we need some
> - * special handling to get the core back into a state where
> - * it is safe to touch it for configuration. As there is
> - * no dedicated reset signal wired up for MX6QDL, we need
> - * to manually force LTSSM into "detect" state before
> - * completely disabling LTSSM, which is a prerequisite for
> - * core configuration.
> - *
> - * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we
> - * have a strong indication that the bootloader activated
> - * the link.
> - */
> - regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
> - regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
> -
> - if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
> - (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
> - val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR);
> - val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
> - val |= PCIE_PL_PFLR_FORCE_LINK;
> - dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val);
> -
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
> - }
> -
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> --
> 2.11.0
>
>
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