The Cortina Gemini has an internal PCI root bus, add this to
the device tree.
Cc: Janos Laube <janos.dev@xxxxxxxxx>
Cc: Paulius Zaleckas <paulius.zaleckas@xxxxxxxxx>
Cc: Hans Ulli Kroll <ulli.kroll@xxxxxxxxxxxxxx>
Cc: Florian Fainelli <f.fainelli@xxxxxxxxx>
Signed-off-by: Linus Walleij <linus.walleij@xxxxxxxxxx>
---
PCI maintainers: this is FYI only, I will funnel this to the ARM
SoC tree once we are done with the PCI driver.
---
arch/arm/boot/dts/gemini.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi
index 405d6cedf409..df5630958038 100644
--- a/arch/arm/boot/dts/gemini.dtsi
+++ b/arch/arm/boot/dts/gemini.dtsi
@@ -99,4 +99,49 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ pci@50000000 {
+ compatible = "cortina,gemini-pci";
+ reg = <0x50000000 0x100>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */
+ <26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */
+ <27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */
+ <28 IRQ_TYPE_LEVEL_HIGH>; /* PCI D */
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ bus-range = <0x00 0x00>; /* Only root bus */
+ /* PCI ranges mappings */
+ ranges = /* 1MiB I/O space 0x50000000-0x500fffff */
+ <0x01000000 0 0 0x50000000 0 0x00100000>,
+ /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
+ <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
+
+ interrupt-map-mask = <0xff00 0 0 7>;
+ /*
+ * The interrupt map is done by sub-device and per-slot.
+ */
+ interrupt-map = <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
+ <0x4900 0 0 2 &pci_intc 1>,
+ <0x4a00 0 0 3 &pci_intc 2>,
+ <0x4b00 0 0 4 &pci_intc 3>,
+ <0x5000 0 0 1 &pci_intc 0>, /* Slot 10 */
+ <0x5100 0 0 2 &pci_intc 1>,
+ <0x5200 0 0 3 &pci_intc 2>,
+ <0x5300 0 0 4 &pci_intc 3>,
+ <0x5800 0 0 1 &pci_intc 0>, /* Slot 11 */
+ <0x5900 0 0 2 &pci_intc 1>,
+ <0x5a00 0 0 3 &pci_intc 2>,
+ <0x5b00 0 0 4 &pci_intc 3>,
+ <0x6000 0 0 1 &pci_intc 0>, /* Slot 12 */
+ <0x6100 0 0 2 &pci_intc 1>,
+ <0x6200 0 0 3 &pci_intc 2>,
+ <0x6300 0 0 4 &pci_intc 3>;
+ pci_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
};
--
2.9.3
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