tree: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/ecam head: f80edf4d6c053d529b4f044f867f8269f0050c72 commit: f80edf4d6c053d529b4f044f867f8269f0050c72 [13/13] PCI: Add MCFG quirks for Cavium ThunderX pass1.x host controller config: arm64-defconfig (attached as .config) compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705 reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout f80edf4d6c053d529b4f044f867f8269f0050c72 # save the attached .config to linux build tree make.cross ARCH=arm64 All warnings (new ones prefixed by >>): In file included from include/linux/pci.h:24:0, from drivers/acpi/pci_mcfg.c:23: >> drivers/acpi/pci_mcfg.c:79:30: warning: left shift count >= width of type [-Wshift-count-overflow] DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M) ^ include/linux/ioport.h:138:13: note: in definition of macro 'DEFINE_RES_NAMED' .start = (_start), \ ^~~~~~ >> include/linux/ioport.h:153:2: note: in expansion of macro 'DEFINE_RES_MEM_NAMED' DEFINE_RES_MEM_NAMED((_start), (_size), NULL) ^~~~~~~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:79:2: note: in expansion of macro 'DEFINE_RES_MEM' DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M) ^~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:82:27: note: in expansion of macro 'THUNDER_PEM_RES' &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \ ^~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:101:2: note: in expansion of macro 'THUNDER_PEM_QUIRK' THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */ ^~~~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:79:30: warning: left shift count >= width of type [-Wshift-count-overflow] DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M) ^ include/linux/ioport.h:139:11: note: in definition of macro 'DEFINE_RES_NAMED' .end = (_start) + (_size) - 1, \ ^~~~~~ >> include/linux/ioport.h:153:2: note: in expansion of macro 'DEFINE_RES_MEM_NAMED' DEFINE_RES_MEM_NAMED((_start), (_size), NULL) ^~~~~~~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:79:2: note: in expansion of macro 'DEFINE_RES_MEM' DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M) ^~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:82:27: note: in expansion of macro 'THUNDER_PEM_RES' &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \ ^~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:101:2: note: in expansion of macro 'THUNDER_PEM_QUIRK' THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */ ^~~~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:79:30: warning: left shift count >= width of type [-Wshift-count-overflow] DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M) ^ include/linux/ioport.h:138:13: note: in definition of macro 'DEFINE_RES_NAMED' .start = (_start), \ ^~~~~~ >> include/linux/ioport.h:153:2: note: in expansion of macro 'DEFINE_RES_MEM_NAMED' DEFINE_RES_MEM_NAMED((_start), (_size), NULL) ^~~~~~~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:79:2: note: in expansion of macro 'DEFINE_RES_MEM' DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M) ^~~~~~~~~~~~~~ drivers/acpi/pci_mcfg.c:84:27: note: in expansion of macro 'THUNDER_PEM_RES' &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \ ^~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:101:2: note: in expansion of macro 'THUNDER_PEM_QUIRK' THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */ ^~~~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:79:30: warning: left shift count >= width of type [-Wshift-count-overflow] DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M) ^ include/linux/ioport.h:139:11: note: in definition of macro 'DEFINE_RES_NAMED' .end = (_start) + (_size) - 1, \ ^~~~~~ >> include/linux/ioport.h:153:2: note: in expansion of macro 'DEFINE_RES_MEM_NAMED' DEFINE_RES_MEM_NAMED((_start), (_size), NULL) ^~~~~~~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:79:2: note: in expansion of macro 'DEFINE_RES_MEM' DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M) ^~~~~~~~~~~~~~ drivers/acpi/pci_mcfg.c:84:27: note: in expansion of macro 'THUNDER_PEM_RES' &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \ ^~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:101:2: note: in expansion of macro 'THUNDER_PEM_QUIRK' THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */ ^~~~~~~~~~~~~~~~~ >> drivers/acpi/pci_mcfg.c:79:30: warning: left shift count >= width of type [-Wshift-count-overflow] DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M) ^ include/linux/ioport.h:138:13: note: in definition of macro 'DEFINE_RES_NAMED' .start = (_start), \ ^~~~~~ >> include/linux/ioport.h:153:2: note: in expansion of macro 'DEFINE_RES_MEM_NAMED' DEFINE_RES_MEM_NAMED((_start), (_size), NULL) ^~~~~~~~~~~~~~~~~~~~ vim +79 drivers/acpi/pci_mcfg.c 935c760e Tomasz Nowicki 2016-06-10 17 * version 2 (GPLv2) along with this source code. 935c760e Tomasz Nowicki 2016-06-10 18 */ 935c760e Tomasz Nowicki 2016-06-10 19 935c760e Tomasz Nowicki 2016-06-10 20 #define pr_fmt(fmt) "ACPI: " fmt 935c760e Tomasz Nowicki 2016-06-10 21 935c760e Tomasz Nowicki 2016-06-10 22 #include <linux/kernel.h> 935c760e Tomasz Nowicki 2016-06-10 @23 #include <linux/pci.h> 935c760e Tomasz Nowicki 2016-06-10 24 #include <linux/pci-acpi.h> b13e44a1 Tomasz Nowicki 2016-09-09 25 #include <linux/pci-ecam.h> 935c760e Tomasz Nowicki 2016-06-10 26 935c760e Tomasz Nowicki 2016-06-10 27 /* Structure to hold entries from the MCFG table */ 935c760e Tomasz Nowicki 2016-06-10 28 struct mcfg_entry { 935c760e Tomasz Nowicki 2016-06-10 29 struct list_head list; 935c760e Tomasz Nowicki 2016-06-10 30 phys_addr_t addr; 935c760e Tomasz Nowicki 2016-06-10 31 u16 segment; 935c760e Tomasz Nowicki 2016-06-10 32 u8 bus_start; 935c760e Tomasz Nowicki 2016-06-10 33 u8 bus_end; 935c760e Tomasz Nowicki 2016-06-10 34 }; 935c760e Tomasz Nowicki 2016-06-10 35 2d76ea5d Tomasz Nowicki 2016-09-09 36 #ifdef CONFIG_PCI_QUIRKS 2d76ea5d Tomasz Nowicki 2016-09-09 37 struct mcfg_fixup { 2d76ea5d Tomasz Nowicki 2016-09-09 38 char oem_id[ACPI_OEM_ID_SIZE + 1]; 2d76ea5d Tomasz Nowicki 2016-09-09 39 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; 2d76ea5d Tomasz Nowicki 2016-09-09 40 u32 oem_revision; 2d76ea5d Tomasz Nowicki 2016-09-09 41 u16 segment; 2d76ea5d Tomasz Nowicki 2016-09-09 42 struct resource bus_range; 2d76ea5d Tomasz Nowicki 2016-09-09 43 struct pci_ecam_ops *ops; 2d76ea5d Tomasz Nowicki 2016-09-09 44 struct resource cfgres; 2d76ea5d Tomasz Nowicki 2016-09-09 45 }; 2d76ea5d Tomasz Nowicki 2016-09-09 46 2d76ea5d Tomasz Nowicki 2016-09-09 47 #define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \ 2d76ea5d Tomasz Nowicki 2016-09-09 48 ((end) - (start) + 1), \ 2d76ea5d Tomasz Nowicki 2016-09-09 49 NULL, IORESOURCE_BUS) 2d76ea5d Tomasz Nowicki 2016-09-09 50 #define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff) 2d76ea5d Tomasz Nowicki 2016-09-09 51 2d76ea5d Tomasz Nowicki 2016-09-09 52 static struct mcfg_fixup mcfg_quirks[] = { 2d76ea5d Tomasz Nowicki 2016-09-09 53 /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */ fb0e9447 Christopher Covington 2016-11-02 54 fb0e9447 Christopher Covington 2016-11-02 55 #define QCOM_ECAM32(seg) \ fb0e9447 Christopher Covington 2016-11-02 56 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops } fb0e9447 Christopher Covington 2016-11-02 57 QCOM_ECAM32(0), fb0e9447 Christopher Covington 2016-11-02 58 QCOM_ECAM32(1), fb0e9447 Christopher Covington 2016-11-02 59 QCOM_ECAM32(2), fb0e9447 Christopher Covington 2016-11-02 60 QCOM_ECAM32(3), fb0e9447 Christopher Covington 2016-11-02 61 QCOM_ECAM32(4), fb0e9447 Christopher Covington 2016-11-02 62 QCOM_ECAM32(5), fb0e9447 Christopher Covington 2016-11-02 63 QCOM_ECAM32(6), fb0e9447 Christopher Covington 2016-11-02 64 QCOM_ECAM32(7), 93c4ddcc Dongdong Liu 2016-12-01 65 93c4ddcc Dongdong Liu 2016-12-01 66 #define HISI_QUAD_DOM(table_id, seg, ops) \ 93c4ddcc Dongdong Liu 2016-12-01 67 { "HISI ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \ 93c4ddcc Dongdong Liu 2016-12-01 68 { "HISI ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \ 93c4ddcc Dongdong Liu 2016-12-01 69 { "HISI ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \ 93c4ddcc Dongdong Liu 2016-12-01 70 { "HISI ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops } 93c4ddcc Dongdong Liu 2016-12-01 71 HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops), 93c4ddcc Dongdong Liu 2016-12-01 72 HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops), 93c4ddcc Dongdong Liu 2016-12-01 73 HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops), 93c4ddcc Dongdong Liu 2016-12-01 74 HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops), 93c4ddcc Dongdong Liu 2016-12-01 75 HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops), 93c4ddcc Dongdong Liu 2016-12-01 76 HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops), 8d65ae34 Tomasz Nowicki 2016-12-01 77 8d65ae34 Tomasz Nowicki 2016-12-01 78 #define THUNDER_PEM_RES(addr, node) \ 8d65ae34 Tomasz Nowicki 2016-12-01 @79 DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M) 8d65ae34 Tomasz Nowicki 2016-12-01 80 #define THUNDER_PEM_QUIRK(rev, node) \ 8d65ae34 Tomasz Nowicki 2016-12-01 81 { "CAVIUM", "THUNDERX", rev, 4 + (10 * node), MCFG_BUS_ANY, \ 8d65ae34 Tomasz Nowicki 2016-12-01 @82 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \ 8d65ae34 Tomasz Nowicki 2016-12-01 83 { "CAVIUM", "THUNDERX", rev, 5 + (10 * node), MCFG_BUS_ANY, \ 8d65ae34 Tomasz Nowicki 2016-12-01 84 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \ 8d65ae34 Tomasz Nowicki 2016-12-01 85 { "CAVIUM", "THUNDERX", rev, 6 + (10 * node), MCFG_BUS_ANY, \ 8d65ae34 Tomasz Nowicki 2016-12-01 86 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \ 8d65ae34 Tomasz Nowicki 2016-12-01 87 { "CAVIUM", "THUNDERX", rev, 7 + (10 * node), MCFG_BUS_ANY, \ 8d65ae34 Tomasz Nowicki 2016-12-01 88 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \ 8d65ae34 Tomasz Nowicki 2016-12-01 89 { "CAVIUM", "THUNDERX", rev, 8 + (10 * node), MCFG_BUS_ANY, \ 8d65ae34 Tomasz Nowicki 2016-12-01 90 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \ 8d65ae34 Tomasz Nowicki 2016-12-01 91 { "CAVIUM", "THUNDERX", rev, 9 + (10 * node), MCFG_BUS_ANY, \ 8d65ae34 Tomasz Nowicki 2016-12-01 92 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) } 8d65ae34 Tomasz Nowicki 2016-12-01 93 /* SoC pass2.x */ 8d65ae34 Tomasz Nowicki 2016-12-01 94 THUNDER_PEM_QUIRK(1, 0UL), 8d65ae34 Tomasz Nowicki 2016-12-01 95 THUNDER_PEM_QUIRK(1, 1UL), f80edf4d Tomasz Nowicki 2016-11-30 96 f80edf4d Tomasz Nowicki 2016-11-30 97 #define THUNDER_ECAM_QUIRK(rev, node) \ f80edf4d Tomasz Nowicki 2016-11-30 98 { "CAVIUM", "THUNDERX", rev, node, MCFG_BUS_ANY, \ f80edf4d Tomasz Nowicki 2016-11-30 99 &pci_thunder_ecam_ops } f80edf4d Tomasz Nowicki 2016-11-30 100 /* SoC pass1.x */ f80edf4d Tomasz Nowicki 2016-11-30 @101 THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */ f80edf4d Tomasz Nowicki 2016-11-30 102 THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */ f80edf4d Tomasz Nowicki 2016-11-30 103 THUNDER_ECAM_QUIRK(2, 0), f80edf4d Tomasz Nowicki 2016-11-30 104 THUNDER_ECAM_QUIRK(2, 1), :::::: The code at line 79 was first introduced by commit :::::: 8d65ae347c5bda1abf0d25e919e0209fca8f5a7a PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller :::::: TO: Tomasz Nowicki <tn@xxxxxxxxxxxx> :::::: CC: Bjorn Helgaas <helgaas@xxxxxxxxxx> --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
Attachment:
.config.gz
Description: application/gzip
