Hi Bjorn Many many thanks for putting this together! [...] > > PCI: Add MCFG quirks for HiSilicon Hip05/06/07 host controllers > > Dongdong's HiSilicon quirks. Here's where it gets interesting. I > moved this to the existing pcie-hisi.c instead of adding > pcie-hisi-acpi.c. I changed the Makefile so we always build > pcie-hisi.c on ARM64. I added ifdefs so we get the quirk code if > CONFIG_ACPI and CONFIG_PCI_QUIRKS and we get the original platform > driver if CONFIG_PCI_HISI. It's possible to have both, and if we > process the MCFG quirk we get the quirk code. > > I'm confused about why the quirk accessors are so much different > than the original accessors. hisi_pcie_acpi_rd_conf() looks much > different than hisi_pcie_cfg_read(). The original driver claims > Hipxx only supports 32-bit config accesses, but the quirk > accessors don't enforce that. Well the main point is that hisi_pcie_acpi_rd_conf() assigned to pci_ops.read whereas hisi_pcie_cfg_read() is assigned to hisi_pcie_host_ops.rd_own_conf. The first one is used to access the whole pci configuration space, whereas the second is dedicated to the root complex 'own' configuration space. As you can see also in hisi_pcie_acpi_rd_conf() we enforce 32b access for the root complex. Now the main issue here is that all the designware based drivers currently use the same instance of pci_ops: http://lxr.free-electrons.com/source/drivers/pci/host/pcie-designware.c#L713 In order to solve this we should turn the designware pci_ops into per driver instances; see my comment in a previous discussion: http://www.spinics.net/lists/linux-pci/msg56097.html Thanks Gab [...] ��.n��������+%������w��{.n�����{���"�)�� jg��� �����ݢj����G���� ���j:+v���w�m������w�������h�����٥
