On Thu, Oct 13, 2016 at 09:16:31AM +0800, Shawn Lin wrote:
> The negotiated lane numbers was incorrectly calculated, fix it.
>
> Fixes: e77f847df54c6b0 ("PCI: rockchip: Add Rockchip PCIe controller support")
> Signed-off-by: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx>
> ---
>
> drivers/pci/host/pcie-rockchip.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index e0b22da..0d69d8c 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -549,7 +549,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>
> /* Check the final link width from negotiated lane counter from MGMT */
> status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
> - status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
> + status = 0x1 << ((status >> PCIE_CORE_PL_CONF_LANE_SHIFT) &
> PCIE_CORE_PL_CONF_LANE_MASK);
> dev_dbg(dev, "current link width is x%d\n", status);
>
Looks good to me:
Reviewed-by: Brian Norris <briannorris@xxxxxxxxxxxx>
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