tree: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-hisi head: f5742eac980f867a02bcd47a164b651be39bf1b2 commit: 24a259625da5ea5937affabc83688c569d65fb58 [28/29] PCI: hisi: Add local struct device pointers config: arm64-allmodconfig (attached as .config) compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705 reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 24a259625da5ea5937affabc83688c569d65fb58 # save the attached .config to linux build tree make.cross ARCH=arm64 All errors (new ones prefixed by >>): drivers/pci/host/pcie-hisi.c: In function 'hisi_cfg_read': drivers/pci/host/pcie-hisi.c:49:20: warning: unused variable 'hisi_pcie' [-Wunused-variable] struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp); ^~~~~~~~~ drivers/pci/host/pcie-hisi.c: In function 'hisi_pcie_probe': >> drivers/pci/host/pcie-hisi.c:180:18: error: 'hisi' undeclared (first use in this function) return PTR_ERR(hisi->subctrl); ^~~~ drivers/pci/host/pcie-hisi.c:180:18: note: each undeclared identifier is reported only once for each function it appears in vim +/hisi +180 drivers/pci/host/pcie-hisi.c 43 struct pcie_soc_ops *soc_ops; 44 }; 45 46 /* HipXX PCIe host only supports 32-bit config access */ 47 static int hisi_cfg_read(struct pcie_port *pp, int where, int size, u32 *val) 48 { > 49 struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp); 50 u32 reg; 51 u32 reg_val; 52 void *walker = ®_val; 53 54 walker += (where & 0x3); 55 reg = where & ~0x3; 56 reg_val = dw_pcie_readl_rc(pp, reg); 57 58 if (size == 1) 59 *val = *(u8 __force *) walker; 60 else if (size == 2) 61 *val = *(u16 __force *) walker; 62 else if (size == 4) 63 *val = reg_val; 64 else 65 return PCIBIOS_BAD_REGISTER_NUMBER; 66 67 return PCIBIOS_SUCCESSFUL; 68 } 69 70 /* HipXX PCIe host only supports 32-bit config access */ 71 static int hisi_cfg_write(struct pcie_port *pp, int where, int size, u32 val) 72 { 73 u32 reg_val; 74 u32 reg; 75 void *walker = ®_val; 76 77 walker += (where & 0x3); 78 reg = where & ~0x3; 79 if (size == 4) 80 dw_pcie_writel_rc(pp, reg, val); 81 else if (size == 2) { 82 reg_val = dw_pcie_readl_rc(pp, reg); 83 *(u16 __force *) walker = val; 84 dw_pcie_writel_rc(pp, reg, reg_val); 85 } else if (size == 1) { 86 reg_val = dw_pcie_readl_rc(pp, reg); 87 *(u8 __force *) walker = val; 88 dw_pcie_writel_rc(pp, reg, reg_val); 89 } else 90 return PCIBIOS_BAD_REGISTER_NUMBER; 91 92 return PCIBIOS_SUCCESSFUL; 93 } 94 95 static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie) 96 { 97 u32 val; 98 99 regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG + 100 0x100 * hisi_pcie->port_id, &val); 101 102 return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); 103 } 104 105 static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie) 106 { 107 u32 val; 108 109 val = dw_pcie_readl_rc(&hisi_pcie->pp, PCIE_SYS_STATE4); 110 return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); 111 } 112 113 static int hisi_pcie_link_up(struct pcie_port *pp) 114 { 115 struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp); 116 117 return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie); 118 } 119 120 static struct pcie_host_ops hisi_pcie_host_ops = { 121 .rd_own_conf = hisi_cfg_read, 122 .wr_own_conf = hisi_cfg_write, 123 .link_up = hisi_pcie_link_up, 124 }; 125 126 static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie, 127 struct platform_device *pdev) 128 { 129 struct pcie_port *pp = &hisi_pcie->pp; 130 struct device *dev = pp->dev; 131 int ret; 132 u32 port_id; 133 134 if (of_property_read_u32(dev->of_node, "port-id", &port_id)) { 135 dev_err(dev, "failed to read port-id\n"); 136 return -EINVAL; 137 } 138 if (port_id > 3) { 139 dev_err(dev, "Invalid port-id: %d\n", port_id); 140 return -EINVAL; 141 } 142 hisi_pcie->port_id = port_id; 143 144 pp->ops = &hisi_pcie_host_ops; 145 146 ret = dw_pcie_host_init(pp); 147 if (ret) { 148 dev_err(dev, "failed to initialize host\n"); 149 return ret; 150 } 151 152 return 0; 153 } 154 155 static int hisi_pcie_probe(struct platform_device *pdev) 156 { 157 struct device *dev = &pdev->dev; 158 struct hisi_pcie *hisi_pcie; 159 struct pcie_port *pp; 160 const struct of_device_id *match; 161 struct resource *reg; 162 struct device_driver *driver; 163 int ret; 164 165 hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL); 166 if (!hisi_pcie) 167 return -ENOMEM; 168 169 pp = &hisi_pcie->pp; 170 pp->dev = dev; 171 172 driver = (pdev->dev).driver; 173 match = of_match_device(driver->of_match_table, dev); 174 hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data; 175 176 hisi_pcie->subctrl = 177 syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl"); 178 if (IS_ERR(hisi_pcie->subctrl)) { 179 dev_err(dev, "cannot get subctrl base\n"); > 180 return PTR_ERR(hisi->subctrl); 181 } 182 183 reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi"); --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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