tree: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-cleanups-wip head: ee559fc5aa013976c4415dbd9c14107b6eebaa10 commit: da1be73f98733b5d99f08e5bf2a1e700f955e39c [76/95] PCI: keystone: Add app register accessors config: arm-multi_v7_defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705 reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout da1be73f98733b5d99f08e5bf2a1e700f955e39c # save the attached .config to linux build tree make.cross ARCH=arm All error/warnings (new ones prefixed by >>): drivers/pci/host/pci-keystone-dw.c: In function 'ks_dw_pcie_handle_legacy_irq': >> drivers/pci/host/pci-keystone-dw.c:54:22: warning: passing argument 1 of 'ks_dw_app_readl' makes pointer from integer without a cast [-Wint-conversion] #define IRQ_STATUS 0x184 ^ >> drivers/pci/host/pci-keystone-dw.c:260:28: note: in expansion of macro 'IRQ_STATUS' pending = ks_dw_app_readl(IRQ_STATUS + (offset << 4)); ^~~~~~~~~~ drivers/pci/host/pci-keystone-dw.c:91:12: note: expected 'struct keystone_pcie *' but argument is of type 'int' static u32 ks_dw_app_readl(struct keystone_pcie *keystone, u32 offset) ^~~~~~~~~~~~~~~ >> drivers/pci/host/pci-keystone-dw.c:260:12: error: too few arguments to function 'ks_dw_app_readl' pending = ks_dw_app_readl(IRQ_STATUS + (offset << 4)); ^~~~~~~~~~~~~~~ drivers/pci/host/pci-keystone-dw.c:91:12: note: declared here static u32 ks_dw_app_readl(struct keystone_pcie *keystone, u32 offset) ^~~~~~~~~~~~~~~ drivers/pci/host/pci-keystone-dw.c: In function 'ks_dw_pcie_setup_rc_app_regs': >> drivers/pci/host/pci-keystone-dw.c:393:2: error: implicit declaration of function 'keystone_app_write' [-Werror=implicit-function-declaration] keystone_app_write(keystone, CMD_STATUS, OB_XLAT_EN_VAL | val); ^~~~~~~~~~~~~~~~~~ cc1: some warnings being treated as errors vim +/ks_dw_app_readl +260 drivers/pci/host/pci-keystone-dw.c 254 void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *keystone, int offset) 255 { 256 struct pcie_port *pp = &keystone->pp; 257 u32 pending; 258 int virq; 259 > 260 pending = ks_dw_app_readl(IRQ_STATUS + (offset << 4)); 261 262 if (BIT(0) & pending) { 263 virq = irq_linear_revmap(keystone->legacy_irq_domain, offset); 264 dev_dbg(pp->dev, ": irq: irq_offset %d, virq %d\n", offset, 265 virq); 266 generic_handle_irq(virq); 267 } 268 269 /* EOI the INTx interrupt */ 270 ks_dw_app_writel(keystone, IRQ_EOI, offset); 271 } 272 273 void ks_dw_pcie_enable_error_irq(struct keystone_pcie *keystone) 274 { 275 ks_dw_app_writel(keystone, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); 276 } 277 278 irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *keystone) 279 { 280 u32 status; 281 282 status = ks_dw_app_readl(keystone, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL; 283 if (!status) 284 return IRQ_NONE; 285 286 if (status & ERR_FATAL_IRQ) 287 dev_err(keystone->pp.dev, "fatal error (status %#010x)\n", 288 status); 289 290 /* Ack the IRQ; status bits are RW1C */ 291 ks_dw_app_writel(keystone, ERR_IRQ_STATUS, status); 292 return IRQ_HANDLED; 293 } 294 295 static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d) 296 { 297 } 298 299 static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d) 300 { 301 } 302 303 static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d) 304 { 305 } 306 307 static struct irq_chip ks_dw_pcie_legacy_irq_chip = { 308 .name = "Keystone-PCI-Legacy-IRQ", 309 .irq_ack = ks_dw_pcie_ack_legacy_irq, 310 .irq_mask = ks_dw_pcie_mask_legacy_irq, 311 .irq_unmask = ks_dw_pcie_unmask_legacy_irq, 312 }; 313 314 static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d, 315 unsigned int irq, irq_hw_number_t hw_irq) 316 { 317 irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip, 318 handle_level_irq); 319 irq_set_chip_data(irq, d->host_data); 320 321 return 0; 322 } 323 324 static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = { 325 .map = ks_dw_pcie_init_legacy_irq_map, 326 .xlate = irq_domain_xlate_onetwocell, 327 }; 328 329 /** 330 * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask 331 * registers 332 * 333 * Since modification of dbi_cs2 involves different clock domain, read the 334 * status back to ensure the transition is complete. 335 */ 336 static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *keystone) 337 { 338 u32 val; 339 340 val = ks_dw_app_readl(keystone, CMD_STATUS); 341 ks_dw_app_writel(keystone, CMD_STATUS, DBI_CS2_EN_VAL | val); 342 343 do { 344 val = ks_dw_app_readl(keystone, CMD_STATUS); 345 } while (!(val & DBI_CS2_EN_VAL)); 346 } 347 348 /** 349 * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode 350 * 351 * Since modification of dbi_cs2 involves different clock domain, read the 352 * status back to ensure the transition is complete. 353 */ 354 static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *keystone) 355 { 356 u32 val; 357 358 val = ks_dw_app_readl(keystone, CMD_STATUS); 359 ks_dw_app_writel(keystone, CMD_STATUS, ~DBI_CS2_EN_VAL & val); 360 361 do { 362 val = ks_dw_app_readl(keystone, CMD_STATUS); 363 } while (val & DBI_CS2_EN_VAL); 364 } 365 366 void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *keystone) 367 { 368 struct pcie_port *pp = &keystone->pp; 369 u32 start = pp->mem->start, end = pp->mem->end; 370 int i, tr_size; 371 u32 val; 372 373 /* Disable BARs for inbound access */ 374 ks_dw_pcie_set_dbi_mode(keystone); 375 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0); 376 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1); 377 ks_dw_pcie_clear_dbi_mode(keystone); 378 379 /* Set outbound translation size per window division */ 380 ks_dw_app_writel(keystone, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7); 381 382 tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M; 383 384 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ 385 for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) { 386 ks_dw_app_writel(keystone, OB_OFFSET_INDEX(i), start | 1); 387 ks_dw_app_writel(keystone, OB_OFFSET_HI(i), 0); 388 start += tr_size; 389 } 390 391 /* Enable OB translation */ 392 val = ks_dw_app_readl(keystone, CMD_STATUS); > 393 keystone_app_write(keystone, CMD_STATUS, OB_XLAT_EN_VAL | val); 394 } 395 396 /** --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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