tree: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-cleanups-wip head: ee559fc5aa013976c4415dbd9c14107b6eebaa10 commit: 3aa03100213456f92786b4c1da302257d6e33e4c [91/95] PCI: rcar-gen2: Add register accessors config: arm-shmobile_defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705 reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 3aa03100213456f92786b4c1da302257d6e33e4c # save the attached .config to linux build tree make.cross ARCH=arm All error/warnings (new ones prefixed by >>): drivers/pci/host/pci-rcar-gen2.c: In function 'rcar_pci_writel': >> drivers/pci/host/pci-rcar-gen2.c:117:12: warning: passing argument 1 of 'iowrite32' makes integer from pointer without a cast [-Wint-conversion] iowrite32(rcar->reg + offset, val); ^~~~ In file included from arch/arm/include/asm/io.h:451:0, from include/linux/io.h:25, from drivers/pci/host/pci-rcar-gen2.c:17: include/asm-generic/io.h:615:19: note: expected 'u32 {aka unsigned int}' but argument is of type 'void *' #define iowrite32 iowrite32 ^ >> include/asm-generic/io.h:616:20: note: in expansion of macro 'iowrite32' static inline void iowrite32(u32 value, volatile void __iomem *addr) ^~~~~~~~~ >> drivers/pci/host/pci-rcar-gen2.c:117:32: warning: passing argument 2 of 'iowrite32' makes pointer from integer without a cast [-Wint-conversion] iowrite32(rcar->reg + offset, val); ^~~ In file included from arch/arm/include/asm/io.h:451:0, from include/linux/io.h:25, from drivers/pci/host/pci-rcar-gen2.c:17: include/asm-generic/io.h:615:19: note: expected 'volatile void *' but argument is of type 'u32 {aka unsigned int}' #define iowrite32 iowrite32 ^ >> include/asm-generic/io.h:616:20: note: in expansion of macro 'iowrite32' static inline void iowrite32(u32 value, volatile void __iomem *addr) ^~~~~~~~~ drivers/pci/host/pci-rcar-gen2.c: In function 'rcar_pci_setup': >> drivers/pci/host/pci-rcar-gen2.c:79:27: warning: passing argument 1 of 'rcar_pci_readl' makes pointer from integer without a cast [-Wint-conversion] #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34) ^ >> drivers/pci/host/pci-rcar-gen2.c:215:23: note: in expansion of macro 'RCAR_USBCTR_REG' val = rcar_pci_readl(RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD; ^~~~~~~~~~~~~~~ drivers/pci/host/pci-rcar-gen2.c:110:12: note: expected 'struct rcar_pci *' but argument is of type 'int' static u32 rcar_pci_readl(struct rcar_pci *rcar, u32 offset) ^~~~~~~~~~~~~~ >> drivers/pci/host/pci-rcar-gen2.c:215:8: error: too few arguments to function 'rcar_pci_readl' val = rcar_pci_readl(RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD; ^~~~~~~~~~~~~~ drivers/pci/host/pci-rcar-gen2.c:110:12: note: declared here static u32 rcar_pci_readl(struct rcar_pci *rcar, u32 offset) ^~~~~~~~~~~~~~ vim +/rcar_pci_readl +215 drivers/pci/host/pci-rcar-gen2.c 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/delay.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> > 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/of_address.h> 20 #include <linux/of_pci.h> 21 #include <linux/pci.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/sizes.h> 25 #include <linux/slab.h> 26 27 /* AHB-PCI Bridge PCI communication registers */ 28 #define RCAR_AHBPCI_PCICOM_OFFSET 0x800 29 30 #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00) 31 #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04) 32 #define RCAR_PCIAHB_PREFETCH0 0x0 33 #define RCAR_PCIAHB_PREFETCH4 0x1 34 #define RCAR_PCIAHB_PREFETCH8 0x2 35 #define RCAR_PCIAHB_PREFETCH16 0x3 36 37 #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10) 38 #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14) 39 #define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1) 40 #define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1) 41 #define RCAR_AHBPCI_WIN1_HOST (1 << 30) 42 #define RCAR_AHBPCI_WIN1_DEVICE (1 << 31) 43 44 #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20) 45 #define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24) 46 #define RCAR_PCI_INT_SIGTABORT (1 << 0) 47 #define RCAR_PCI_INT_SIGRETABORT (1 << 1) 48 #define RCAR_PCI_INT_REMABORT (1 << 2) 49 #define RCAR_PCI_INT_PERR (1 << 3) 50 #define RCAR_PCI_INT_SIGSERR (1 << 4) 51 #define RCAR_PCI_INT_RESERR (1 << 5) 52 #define RCAR_PCI_INT_WIN1ERR (1 << 12) 53 #define RCAR_PCI_INT_WIN2ERR (1 << 13) 54 #define RCAR_PCI_INT_A (1 << 16) 55 #define RCAR_PCI_INT_B (1 << 17) 56 #define RCAR_PCI_INT_PME (1 << 19) 57 #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \ 58 RCAR_PCI_INT_SIGRETABORT | \ 59 RCAR_PCI_INT_SIGRETABORT | \ 60 RCAR_PCI_INT_REMABORT | \ 61 RCAR_PCI_INT_PERR | \ 62 RCAR_PCI_INT_SIGSERR | \ 63 RCAR_PCI_INT_RESERR | \ 64 RCAR_PCI_INT_WIN1ERR | \ 65 RCAR_PCI_INT_WIN2ERR) 66 67 #define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30) 68 #define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0) 69 #define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1) 70 #define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2) 71 #define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7) 72 #define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17) 73 #define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \ 74 RCAR_AHB_BUS_MMODE_BYTE_BURST | \ 75 RCAR_AHB_BUS_MMODE_WR_INCR | \ 76 RCAR_AHB_BUS_MMODE_HBUS_REQ | \ 77 RCAR_AHB_BUS_SMODE_READYCTR) 78 > 79 #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34) 80 #define RCAR_USBCTR_USBH_RST (1 << 0) 81 #define RCAR_USBCTR_PCICLK_MASK (1 << 1) 82 #define RCAR_USBCTR_PLL_RST (1 << 2) 83 #define RCAR_USBCTR_DIRPD (1 << 8) 84 #define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9) 85 #define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10) 86 #define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10) 87 #define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10) 88 #define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10) 89 #define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10) 90 91 #define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40) 92 #define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0) 93 #define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1) 94 #define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12) 95 96 #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48) 97 98 struct rcar_pci { 99 struct device *dev; 100 void __iomem *reg; 101 struct resource mem_res; 102 struct resource *cfg_res; 103 unsigned busnr; 104 int irq; 105 unsigned long window_size; 106 unsigned long window_addr; 107 unsigned long window_pci; 108 }; 109 110 static u32 rcar_pci_readl(struct rcar_pci *rcar, u32 offset) 111 { 112 return ioread32(rcar->reg + offset); 113 } 114 115 static void rcar_pci_writel(struct rcar_pci *rcar, u32 offset, u32 val) 116 { > 117 iowrite32(rcar->reg + offset, val); 118 } 119 120 /* PCI configuration space operations */ 121 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn, 122 int where) 123 { 124 struct pci_sys_data *sys = bus->sysdata; 125 struct rcar_pci *rcar = sys->private_data; 126 int slot, val; 127 128 if (sys->busnr != bus->number || PCI_FUNC(devfn)) 129 return NULL; 130 131 /* Only one EHCI/OHCI device built-in */ 132 slot = PCI_SLOT(devfn); 133 if (slot > 2) 134 return NULL; 135 136 /* bridge logic only has registers to 0x40 */ 137 if (slot == 0x0 && where >= 0x40) 138 return NULL; 139 140 val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG : 141 RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG; 142 143 rcar_pci_writel(rcar, RCAR_AHBPCI_WIN1_CTR_REG, val); 144 return rcar->reg + (slot >> 1) * 0x100 + where; 145 } 146 147 /* PCI interrupt mapping */ 148 static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 149 { 150 struct pci_sys_data *sys = dev->bus->sysdata; 151 struct rcar_pci *rcar = sys->private_data; 152 int irq; 153 154 irq = of_irq_parse_and_map_pci(dev, slot, pin); 155 if (!irq) 156 irq = rcar->irq; 157 158 return irq; 159 } 160 161 #ifdef CONFIG_PCI_DEBUG 162 /* if debug enabled, then attach an error handler irq to the bridge */ 163 164 static irqreturn_t rcar_pci_err_irq(int irq, void *pw) 165 { 166 struct rcar_pci *rcar = pw; 167 u32 status = rcar_pci_read(rcar, RCAR_PCI_INT_STATUS_REG); 168 169 if (status & RCAR_PCI_INT_ALLERRORS) { 170 dev_err(rcar->dev, "error irq: status %08x\n", status); 171 172 /* clear the error(s) */ 173 rcar_pci_writel(rcar, RCAR_PCI_INT_STATUS_REG, 174 status & RCAR_PCI_INT_ALLERRORS); 175 return IRQ_HANDLED; 176 } 177 178 return IRQ_NONE; 179 } 180 181 static void rcar_pci_setup_errirq(struct rcar_pci *rcar) 182 { 183 int ret; 184 u32 val; 185 186 ret = devm_request_irq(rcar->dev, rcar->irq, rcar_pci_err_irq, 187 IRQF_SHARED, "error irq", rcar); 188 if (ret) { 189 dev_err(rcar->dev, "cannot claim IRQ for error handling\n"); 190 return; 191 } 192 193 val = rcar_pci_readl(rcar, RCAR_PCI_INT_ENABLE_REG); 194 val |= RCAR_PCI_INT_ALLERRORS; 195 rcar_pci_writel(rcar, RCAR_PCI_INT_ENABLE_REG, val); 196 } 197 #else 198 static inline void rcar_pci_setup_errirq(struct rcar_pci *rcar) { } 199 #endif 200 201 /* PCI host controller setup */ 202 static int rcar_pci_setup(int nr, struct pci_sys_data *sys) 203 { 204 struct rcar_pci *rcar = sys->private_data; 205 u32 val; 206 int ret; 207 208 pm_runtime_enable(rcar->dev); 209 pm_runtime_get_sync(rcar->dev); 210 211 val = rcar_pci_readl(rcar, RCAR_PCI_UNIT_REV_REG); 212 dev_info(rcar->dev, "PCI: bus%u revision %x\n", sys->busnr, val); 213 214 /* Disable Direct Power Down State and assert reset */ > 215 val = rcar_pci_readl(RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD; 216 val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST; 217 rcar_pci_writel(rcar, RCAR_USBCTR_REG, val); 218 udelay(4); --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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