Thanks for the tip Brian, I was able to test it too (for some reason
my system didn't fall apart on retraining the link to 5GT/s).
Sending out new one shortly.
On Thu, Sep 22, 2016 at 2:56 PM, Rajat Jain <rajatja@xxxxxxxxxx> wrote:
> On Thu, Sep 22, 2016 at 2:14 PM, Brian Norris <briannorris@xxxxxxxxxxxx> wrote:
>> (Nit: I think the $subject is typically 'PCI: rockchip: ...'.)
>>
>> Hi Rajat,
>>
>> On Thu, Sep 22, 2016 at 02:00:27PM -0700, Rajat Jain wrote:
>>> The register value gets lost on a Link speed/width change, and the
>>> ideal fix should reprogram this on that event (refer "Link Bandwidth
>>> Management Interrupt Enable" & "Link Autonomous Bandwidth Interrupt Enable"
>>> in link control reg?).
>>
>> Oh, that that reminds me (sorry for not noticing this earlier): Rockchip
>> did add handling of those two interrupt bits. See:
>>
>> } else if (reg & PCIE_CLIENT_INT_PHY) {
>> dev_dbg(dev, "phy link changes\n");
>> rockchip_pcie_clr_bw_int(rockchip);
>> }
>
> Oh I did not notice this. I'll try it out..
>
>>
>> Do you ever see such interrupts? In any case, it's possible we could do
>> the re-programming there, just to be sure, though I'm not sure we can
>> test it well.
>>
>> Brian
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