tree: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-rockchip-wip head: a70ccae5d373979646351256db4576204dbfd1ae commit: d320e87de2415dd4ae60d710b2747d0546e2b3a2 [11/17] Move CSR bases into definition. config: arm-allmodconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609 reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout d320e87de2415dd4ae60d710b2747d0546e2b3a2 # save the attached .config to linux build tree make.cross ARCH=arm All error/warnings (new ones prefixed by >>): drivers/pci/host/pcie-rockchip.c: In function 'rockchip_pcie_init_port': drivers/pci/host/pcie-rockchip.c:418:8: error: 'PCIE_CLIENT_ARI_ENABLE' undeclared (first use in this function) PCIE_CLIENT_ARI_ENABLE | ^ drivers/pci/host/pcie-rockchip.c:418:8: note: each undeclared identifier is reported only once for each function it appears in drivers/pci/host/pcie-rockchip.c:420:8: error: 'PCIE_CLIENT_MODE_RC' undeclared (first use in this function) PCIE_CLIENT_MODE_RC | ^ >> drivers/pci/host/pcie-rockchip.c:508:12: error: 'PCIE_CORE_LCS_RETRAIN_LINK' undeclared (first use in this function) status |= PCIE_CORE_LCS_RETRAIN_LINK; ^ drivers/pci/host/pcie-rockchip.c: In function 'rockchip_pcie_prog_ob_atu': >> drivers/pci/host/pcie-rockchip.c:971:12: warning: assignment makes pointer from integer without a cast [-Wint-conversion] aw_offset = (region_no << OB_REG_SIZE_SHIFT); ^ >> drivers/pci/host/pcie-rockchip.c:978:2: error: implicit declaration of function 'rockchip_pcie_writel' [-Werror=implicit-function-declaration] rockchip_pcie_writel(rockchip, ob_addr_0, ^ drivers/pci/host/pcie-rockchip.c: In function 'rockchip_pcie_prog_ib_atu': drivers/pci/host/pcie-rockchip.c:1005:12: warning: assignment makes pointer from integer without a cast [-Wint-conversion] aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT); ^ cc1: some warnings being treated as errors vim +/PCIE_CORE_LCS_RETRAIN_LINK +508 drivers/pci/host/pcie-rockchip.c 412 return err; 413 } 414 415 rockchip_pcie_write(rockchip, 416 PCIE_CLIENT_CONF_ENABLE | 417 PCIE_CLIENT_LINK_TRAIN_ENABLE | > 418 PCIE_CLIENT_ARI_ENABLE | 419 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) | 420 PCIE_CLIENT_MODE_RC | 421 PCIE_CLIENT_GEN_SEL_2, 422 PCIE_CLIENT_BASE); 423 424 err = phy_power_on(rockchip->phy); 425 if (err) { 426 dev_err(dev, "fail to power on phy, err %d\n", err); 427 return err; 428 } 429 430 err = reset_control_deassert(rockchip->core_rst); 431 if (err) { 432 dev_err(dev, "deassert core_rst err %d\n", err); 433 return err; 434 } 435 436 err = reset_control_deassert(rockchip->mgmt_rst); 437 if (err) { 438 dev_err(dev, "deassert mgmt_rst err %d\n", err); 439 return err; 440 } 441 442 err = reset_control_deassert(rockchip->mgmt_sticky_rst); 443 if (err) { 444 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); 445 return err; 446 } 447 448 err = reset_control_deassert(rockchip->pipe_rst); 449 if (err) { 450 dev_err(dev, "deassert pipe_rst err %d\n", err); 451 return err; 452 } 453 454 /* 455 * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before 456 * enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't 457 * reliable and enabling ASPM doesn't work. This is a controller 458 * bug we need to work around. 459 */ 460 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2); 461 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2); 462 463 /* Enable Gen1 training */ 464 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, 465 PCIE_CLIENT_BASE); 466 467 gpiod_set_value(rockchip->ep_gpio, 1); 468 469 /* 500ms timeout value should be enough for Gen1/2 training */ 470 timeout = jiffies + msecs_to_jiffies(500); 471 472 for (;;) { 473 status = rockchip_pcie_read(rockchip, 474 PCIE_CLIENT_BASIC_STATUS1); 475 if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) & 476 PCIE_CLIENT_LINK_STATUS_MASK) == 477 PCIE_CLIENT_LINK_STATUS_UP) { 478 dev_dbg(dev, "PCIe link training gen1 pass!\n"); 479 break; 480 } 481 482 msleep(20); 483 484 if (!time_before(jiffies, timeout)) { 485 err = -ETIMEDOUT; 486 break; 487 } 488 } 489 490 /* Double check gen1 training */ 491 if (err) { 492 status = rockchip_pcie_read(rockchip, 493 PCIE_CLIENT_BASIC_STATUS1); 494 err = (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) & 495 PCIE_CLIENT_LINK_STATUS_MASK) == 496 PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT; 497 if (err) { 498 dev_err(dev, "PCIe link training gen1 timeout!\n"); 499 return err; 500 } 501 } 502 503 /* 504 * Enable retrain for gen2. This should be configured only after 505 * gen1 finished. 506 */ 507 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); > 508 status |= PCIE_CORE_LCS_RETRAIN_LINK; 509 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 510 511 timeout = jiffies + msecs_to_jiffies(500); --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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