On Thu, Jul 28, 2016 at 04:15:31PM +0800, wangyijing wrote: > Hi all, we found a question about PCIe cacheline, the cacheline here is mean the > configure space register at offset 0x0C in type 0 and type 1 configure space header. > > We did a hotplug in our platform for PCIe SAS controller, this sas controller has > SSD disks and the disk sector is 520 bytes. Defaultly, BIOS set cacheline size to > 64bytes, we test the IO read(io size is 128k/256k), the bandwith is 6G. > After hotplug, the cacheline size in SAS controller changes to 0(default after #RST), > and we test the IO read again, the bandwith changes to 5.2G. > > We Tested other SAS controller which is not 520 bytes sector, we didn't found this issue, > and I grep the PCI_CACHE_LINE_SIZE in kernel, I found most of code change the PCI_CACHE_LINE_SIZE > are device driver, like net, ata, and some arm pci controller. > > In PCI 3.0 spec, I found there are descriptions about cacheline size releated to performance, > but in PCIe 3.0 spec, there is nothing related to cacheline size. Not quite true: sec 7.5.1.3 of PCIe r3.0 says: This field [Cache Line Size] is implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no effect on any PCI Express device behavior. Unless your SAS controller is doing something wrong, I suspect something other than Cache Line Size is responsible for the difference in performance. After hot-add of your controller, Cache Line Size is probably zero because Linux doesn't set it. What happens if you set it manually using "setpci"? Does that affect the performance? You might look at the MPS and MRRS settings in the two scenarios also. You could try collecting the output of "lspci -vvxxx" for the whole system in the default case and again after the hotplug, and then compare the two for differences. Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
