Re: [PATCH v3 2/2] PCI: Rockchip: Add Rockchip PCIe controller support

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Hi,

[auto build test WARNING on pci/next]
[also build test WARNING on v4.7-rc3 next-20160616]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Shawn-Lin/Documentation-bindings-add-dt-doc-for-Rockchip-PCIe-controller/20160616-095337
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 5.3.1-8) 5.3.1 20160205
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm64 

Note: it may well be a FALSE warning. FWIW you are at least aware of it now.
http://gcc.gnu.org/wiki/Better_Uninitialized_Warnings

All warnings (new ones prefixed by >>):

   drivers/pci/host/pcie-rockchip.c: In function 'rockchip_pcie_probe':
>> drivers/pci/host/pcie-rockchip.c:995:6: warning: 'mem_size' may be used uninitialized in this function [-Wmaybe-uninitialized]
     u32 mem_size;
         ^
>> drivers/pci/host/pcie-rockchip.c:1094:9: warning: 'mem_bus_addr' may be used uninitialized in this function [-Wmaybe-uninitialized]
      err = rockchip_pcie_prog_ob_atu(port, reg_no + 1,
            ^
>> drivers/pci/host/pcie-rockchip.c:993:6: warning: 'io_size' may be used uninitialized in this function [-Wmaybe-uninitialized]
     u32 io_size;
         ^
>> drivers/pci/host/pcie-rockchip.c:1115:9: warning: 'io_bus_addr' may be used uninitialized in this function [-Wmaybe-uninitialized]
      err = rockchip_pcie_prog_ob_atu(port,
            ^
>> drivers/pci/host/pcie-rockchip.c:1128:26: warning: 'busn' may be used uninitialized in this function [-Wmaybe-uninitialized]
     port->root_bus_nr = busn->start;
                             ^

vim +/mem_size +995 drivers/pci/host/pcie-rockchip.c

   987		struct resource_entry *win;
   988		resource_size_t io_base;
   989		struct resource	*busn;
   990		struct resource	*mem;
   991		struct resource	*io;
   992		phys_addr_t io_bus_addr;
 > 993		u32 io_size;
   994		phys_addr_t mem_bus_addr;
 > 995		u32 mem_size;
   996		int reg_no;
   997		int err = 0;
   998		int offset = 0;
   999	
  1000		LIST_HEAD(res);
  1001	
  1002		if (!dev->of_node)
  1003			return -ENODEV;
  1004	
  1005		port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
  1006		if (!port)
  1007			return -ENOMEM;
  1008	
  1009		port->dev = dev;
  1010	
  1011		err = rockchip_pcie_parse_dt(port);
  1012		if (err)
  1013			return err;
  1014	
  1015		err = clk_prepare_enable(port->aclk_pcie);
  1016		if (err) {
  1017			dev_err(dev, "Unable to enable aclk_pcie clock.\n");
  1018			goto err_aclk_pcie;
  1019		}
  1020	
  1021		err = clk_prepare_enable(port->aclk_perf_pcie);
  1022		if (err) {
  1023			dev_err(dev, "Unable to enable aclk_perf_pcie clock.\n");
  1024			goto err_aclk_perf_pcie;
  1025		}
  1026	
  1027		err = clk_prepare_enable(port->hclk_pcie);
  1028		if (err) {
  1029			dev_err(dev, "Unable to enable hclk_pcie clock.\n");
  1030			goto err_hclk_pcie;
  1031		}
  1032	
  1033		err = clk_prepare_enable(port->clk_pcie_pm);
  1034		if (err) {
  1035			dev_err(dev, "Unable to enable hclk_pcie clock.\n");
  1036			goto err_pcie_pm;
  1037		}
  1038	
  1039		err = rockchip_pcie_set_vpcie(port);
  1040		if (err) {
  1041			dev_err(port->dev, "Fail to set vpcie regulator.\n");
  1042			goto err_set_vpcie;
  1043		}
  1044	
  1045		err = rockchip_pcie_init_port(port);
  1046		if (err)
  1047			goto err_vpcie;
  1048	
  1049		platform_set_drvdata(pdev, port);
  1050	
  1051		rockchip_pcie_enable_interrupts(port);
  1052	
  1053		err = rockchip_pcie_init_irq_domain(port);
  1054		if (err < 0)
  1055			goto err_vpcie;
  1056	
  1057		err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
  1058						       &res, &io_base);
  1059		if (err)
  1060			goto err_vpcie;
  1061	
  1062		/* Get the I/O and memory ranges from DT */
  1063		resource_list_for_each_entry(win, &res) {
  1064			switch (resource_type(win->res)) {
  1065			case IORESOURCE_IO:
  1066				io = win->res;
  1067				io->name = "I/O";
  1068				io_size = resource_size(io);
  1069				io_bus_addr = io->start - win->offset;
  1070				err = pci_remap_iospace(io, io_base);
  1071				if (err) {
  1072					dev_warn(port->dev, "error %d: failed to map resource %pR\n",
  1073						 err, io);
  1074					continue;
  1075				}
  1076				break;
  1077			case IORESOURCE_MEM:
  1078				mem = win->res;
  1079				mem->name = "MEM";
  1080				mem_size = resource_size(mem);
  1081				mem_bus_addr = mem->start - win->offset;
  1082				break;
  1083			case 0:
  1084				break;
  1085			case IORESOURCE_BUS:
  1086				busn = win->res;
  1087				break;
  1088			default:
  1089				continue;
  1090			}
  1091		}
  1092	
  1093		for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
> 1094			err = rockchip_pcie_prog_ob_atu(port, reg_no + 1,
  1095							AXI_WRAPPER_MEM_WRITE,
  1096							20 - 1,
  1097							mem_bus_addr +
  1098								(reg_no << 20),
  1099							0);
  1100			if (err) {
  1101				dev_err(dev, "Program RC mem outbound atu failed\n");
  1102				goto err_vpcie;
  1103			}
  1104		}
  1105	
  1106		err = rockchip_pcie_prog_ib_atu(port, 2, 32 - 1, 0x0, 0);
  1107		if (err) {
  1108			dev_err(dev, "Program RC mem inbound atu failed\n");
  1109			goto err_vpcie;
  1110		}
  1111	
  1112		offset = mem_size >> 20;
  1113	
  1114		for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
> 1115			err = rockchip_pcie_prog_ob_atu(port,
  1116							reg_no + 1 + offset,
  1117							AXI_WRAPPER_IO_WRITE,
  1118							20 - 1,
  1119							io_bus_addr +
  1120								(reg_no << 20),
  1121							0);
  1122			if (err) {
  1123				dev_err(dev, "Program RC io outbound atu failed\n");
  1124				goto err_vpcie;
  1125			}
  1126		}
  1127	
> 1128		port->root_bus_nr = busn->start;
  1129	
  1130		bus = pci_scan_root_bus(&pdev->dev, 0,
  1131					&rockchip_pcie_ops, port, &res);

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Attachment: .config.gz
Description: Binary data


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