Hello, Thanks for your review! On Thu, 02 Jun 2016 11:35:38 +0200, Arnd Bergmann wrote: > On Thursday, June 2, 2016 11:09:43 AM CEST Thomas Petazzoni wrote: > > + ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ > > + 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ > > > > Any reason for not having a 64-bit MEM prefetchable area in the example? > Does the host not support that? I'll have to admit I am not sure how to find this out from the datasheet. My datasheet says about the PCIe controller: """ 64-bit PCIe address and system address space for outbound transactions """ So I guess this would indicate that a 64-bit MEM area is possible. However, since anyway the area used above is at 0xe8000000 for a length of 0x1000000, what would be the benefit of declaring this range as a 64-bit one ? Regarding the prefetchable aspect, I couldn't find any reference in the datasheet. However, the original driver code explicitly errors out if there is no non-prefetchable memory area, so I guess prefetchable areas is not supported. In of_bus_pci_get_flags(), both the 32-bit and 64-bit cases are handled in the same way, so is this distinction actually being used by the kernel? Thomas -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
