On Thu, May 26, 2016 at 12:45:57PM +0200, Lukas Wunner wrote: > > The PCI PM specification version 1.2 says this in chapter 4.2 (page 37): > > > > There is a minimum time requirement of 50 ms which must be provided by > > system software between when the bus is switched from B2 to B0 and > > when a function on the bus is accessed to allow time for the clock to > > start up and the bus to settle. > > But why do we wait 50 ms when *suspending*, i.e. going from B0 to B2? I guess because PCI requires delays of 10ms for both directions D0 <-> D3hot (see pci_raw_set_power_state()). > (Assuming B2 is the state when the bridge goes to D3hot, which I'm not > sure of. The spec says that the bus state may optionally be B3 if the > bridge is in D3hot.) B3 is the state where the bus goes when it's power is removed so I would expect that to require also the 50ms even though the spec does not explicitly say so. > > Not sure how much of that still applies to modern hardware. > > Could you ask hardware engineers at Intel what the bus state is on > modern chipsets (say, ILK or newer) and Thunderbolt ports to clarify > this? I can try but it is not always easy to find the right person in company as big as Intel. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
