On Wed, Mar 16, 2016 at 10:51:58AM -0600, Stephen Warren wrote:
> On 03/08/2016 08:48 AM, Thierry Reding wrote:
> > From: Thierry Reding <treding@xxxxxxxxxx>
> >
> > Changes to the pad controller device tree binding have required that
> > each lane be associated with a separate PHY.
>
> I still don't think this has anything to do with DT bindings. Rather, the
> definition of a PHY (in HW and the Linux PHY subsystem) is a single lane.
> That fact then requires drivers to support a PHY per lane rather than a
> single multi-lane PHY, and equally means the DT bindings must be written
> according to the correct definition of a PHY.
>
> Still, I suppose the commit description is fine as is.
I've reworded the commit message to give a more accurate rationale for
the change. I'll be posting a v5 soon.
> > Update the PCI host bridge
> > device tree binding to allow each root port to define the list of PHYs
> > required to drive the lanes associated with it.
>
> > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
>
> > +Required properties for Tegra124 and later:
> > +- phys: Must contain an phandle to a PHY for each entry in phy-names.
> > +- phy-names: Must include an entry for each active lane. Note that the number
> > + of entries does not have to (though usually will) be equal to the specified
> > + number of lanes in the nvidia,num-lanes property. Entries are of the form
> > + "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
>
> When would the number of PHYs not equal the number of lanes? I thought the
> whole point of this patch was to switch to per-lane PHYs? Perhaps I'm just
> misremembering some exception, so there may be no need to change this.
This is useful to support the case where we want to connect a x1 or x2
device to a root port that is configured to drive more lanes. It's a
rather unusual configuration, but it would be possible for example to
have an onboard x1 ethernet card, but the board layout is such that it
runs in x1/x2 mode, with the ethernet card connected to the x2 port.
> > Example:
> >
> > SoC DTSI:
> > @@ -169,6 +179,9 @@ SoC DTSI:
> > ranges;
> >
> > nvidia,num-lanes = <2>;
> > +
> > + phys = <&{/padctl@0,7009f000/pads/pcie/pcie-4}>;
> > + phy-names = "pcie-0";
> > };
>
> The example shows a Tegra20 PCIe controller, yet includes
> Tegra124-or-greater properties. That seems a bit odd. Should the changes to
> the example be dropped, or does "Required properties for Tegra124 and later"
> mean "Required for T124+, optional for earlier chips"?
I've annotated these properties with "for Tegra124 and later", hopefully
that clarifies that these properties are only valid on Tegra124 and
later chips. The reason is that earlier (Tegra114 didn't support PCIe,
Tegra30 and Tegra20 did but had PHY registers within the PCI host bridge
I/O memory).
Thierry
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